<acrn-config board="adl-asrock">
  <BIOS_INFO>
	BIOS Information
	Vendor: American Megatrends International, LLC.
	Version: P1.20B
	Release Date: 10/14/2022
	BIOS Revision: 5.25
	</BIOS_INFO>
  <BASE_BOARD_INFO>
	Base Board Information
	Manufacturer: ASRock Industrial
	Product Name: DSB-1210-WT
	Version: To Be Filled By O.E.M.
	</BASE_BOARD_INFO>
  <PCI_DEVICE>
	00:00.0 Host bridge: Intel Corporation 12th Gen Core Processor Host Bridge/DRAM Registers (rev 02)
	Region 3: Memory at &lt;ignored&gt; (32-bit, non-prefetchable)
	00:02.0 VGA compatible controller: Intel Corporation AlderLake-S GT1 (rev 0c)
	Region 0: Memory at 6000000000 (64-bit, non-prefetchable) [size=16M]
	Region 2: Memory at 4000000000 (64-bit, prefetchable) [size=256M]
	Region 0: Memory at 0000004010000000 (64-bit, non-prefetchable)
	Region 2: Memory at 0000004020000000 (64-bit, prefetchable)
	00:06.0 PCI bridge: Intel Corporation 12th Gen Core Processor PCI Express x4 Controller #0 (rev 02)
	00:14.0 USB controller: Intel Corporation Alder Lake-S PCH USB 3.2 Gen 2x2 XHCI Controller (rev 11)
	Region 0: Memory at 6001100000 (64-bit, non-prefetchable) [size=64K]
	00:14.2 RAM memory: Intel Corporation Alder Lake-S PCH Shared SRAM (rev 11)
	Region 0: Memory at 6001114000 (64-bit, non-prefetchable) [disabled] [size=16K]
	Region 2: Memory at 600111c000 (64-bit, non-prefetchable) [disabled] [size=4K]
	00:16.0 Communication controller: Intel Corporation Alder Lake-S PCH HECI Controller #1 (rev 11)
	Region 0: Memory at 600111b000 (64-bit, non-prefetchable) [size=4K]
	00:16.3 Serial controller: Intel Corporation Device 7aeb (rev 11)
	Region 1: Memory at 81304000 (32-bit, non-prefetchable) [size=4K]
	00:17.0 SATA controller: Intel Corporation Alder Lake-S PCH SATA Controller [AHCI Mode] (rev 11)
	Region 0: Memory at 81300000 (32-bit, non-prefetchable) [size=8K]
	Region 1: Memory at 81303000 (32-bit, non-prefetchable) [size=256]
	Region 5: Memory at 81302000 (32-bit, non-prefetchable) [size=2K]
	00:1c.0 PCI bridge: Intel Corporation Alder Lake-S PCH PCI Express Root Port #1 (rev 11)
	00:1c.2 PCI bridge: Intel Corporation Device 7aba (rev 11)
	00:1c.3 PCI bridge: Intel Corporation Device 7abb (rev 11)
	00:1c.4 PCI bridge: Intel Corporation Alder Lake-S PCH PCI Express Root Port #5 (rev 11)
	00:1c.7 PCI bridge: Intel Corporation Alder Lake-S PCH PCI Express Root Port #8 (rev 11)
	00:1d.0 PCI bridge: Intel Corporation Alder Lake-S PCH PCI Express Root Port #9 (rev 11)
	00:1d.6 PCI bridge: Intel Corporation Device 7ab6 (rev 11)
	00:1e.0 Communication controller: Intel Corporation Alder Lake-S PCH Serial IO UART #0 (rev 11)
	Region 0: Memory at 4017000000 (64-bit, non-prefetchable) [size=4K]
	00:1e.3 Serial bus controller: Intel Corporation Alder Lake-S PCH Serial IO SPI Controller #1 (rev 11)
	Region 0: Memory at 4017001000 (64-bit, non-prefetchable) [virtual] [size=4K]
	00:1f.0 ISA bridge: Intel Corporation Device 7a90 (rev 11)
	00:1f.3 Audio device: Intel Corporation Alder Lake-S HD Audio Controller (rev 11)
	Region 0: Memory at 6001110000 (64-bit, non-prefetchable) [size=16K]
	Region 4: Memory at 6001000000 (64-bit, non-prefetchable) [size=1M]
	00:1f.4 SMBus: Intel Corporation Alder Lake-S PCH SMBus Controller (rev 11)
	Region 0: Memory at 6001118000 (64-bit, non-prefetchable) [size=256]
	00:1f.5 Serial bus controller: Intel Corporation Alder Lake-S PCH SPI Controller (rev 11)
	Region 0: Memory at 81305000 (32-bit, non-prefetchable) [size=4K]
	01:00.0 Non-Volatile memory controller: Kingston Technology Company, Inc. OM3PDP3 NVMe SSD (rev 01)
	Region 0: Memory at 81200000 (64-bit, non-prefetchable) [size=16K]
	03:00.0 Ethernet controller: Intel Corporation Ethernet Controller I225-LM (rev 03)
	Region 0: Memory at 81000000 (32-bit, non-prefetchable) [size=1M]
	Region 3: Memory at 81100000 (32-bit, non-prefetchable) [size=16K]
	04:00.0 Ethernet controller: Intel Corporation Ethernet Controller I225-LM (rev 03)
	Region 0: Memory at 80e00000 (32-bit, non-prefetchable) [size=1M]
	Region 3: Memory at 80f00000 (32-bit, non-prefetchable) [size=16K]
	05:00.0 Ethernet controller: Intel Corporation Ethernet Controller I225-LM (rev 03)
	Region 0: Memory at 80c00000 (32-bit, non-prefetchable) [size=1M]
	Region 3: Memory at 80d00000 (32-bit, non-prefetchable) [size=16K]
	06:00.0 Ethernet controller: Intel Corporation Ethernet Controller I225-LM (rev 03)
	Region 0: Memory at 80a00000 (32-bit, non-prefetchable) [size=1M]
	Region 3: Memory at 80b00000 (32-bit, non-prefetchable) [size=16K]
	08:00.0 Ethernet controller: Intel Corporation Ethernet Controller I225-LM (rev 03)
	Region 0: Memory at 80800000 (32-bit, non-prefetchable) [size=1M]
	Region 3: Memory at 80900000 (32-bit, non-prefetchable) [size=16K]
	</PCI_DEVICE>
  <PCI_VID_PID>
	00:00.0 0600: 8086:4668 (rev 02)
	00:02.0 0300: 8086:4680 (rev 0c)
	00:06.0 0604: 8086:464d (rev 02)
	00:14.0 0c03: 8086:7ae0 (rev 11)
	00:14.2 0500: 8086:7aa7 (rev 11)
	00:16.0 0780: 8086:7ae8 (rev 11)
	00:16.3 0700: 8086:7aeb (rev 11)
	00:17.0 0106: 8086:7ae2 (rev 11)
	00:1c.0 0604: 8086:7ab8 (rev 11)
	00:1c.2 0604: 8086:7aba (rev 11)
	00:1c.3 0604: 8086:7abb (rev 11)
	00:1c.4 0604: 8086:7abc (rev 11)
	00:1c.7 0604: 8086:7abf (rev 11)
	00:1d.0 0604: 8086:7ab0 (rev 11)
	00:1d.6 0604: 8086:7ab6 (rev 11)
	00:1e.0 0780: 8086:7aa8 (rev 11)
	00:1e.3 0c80: 8086:7aab (rev 11)
	00:1f.0 0601: 8086:7a90 (rev 11)
	00:1f.3 0403: 8086:7ad0 (rev 11)
	00:1f.4 0c05: 8086:7aa3 (rev 11)
	00:1f.5 0c80: 8086:7aa4 (rev 11)
	01:00.0 0108: 2646:500d (rev 01)
	03:00.0 0200: 8086:15f2 (rev 03)
	04:00.0 0200: 8086:15f2 (rev 03)
	05:00.0 0200: 8086:15f2 (rev 03)
	06:00.0 0200: 8086:15f2 (rev 03)
	08:00.0 0200: 8086:15f2 (rev 03)
	</PCI_VID_PID>
  <WAKE_VECTOR_INFO>
	#define WAKE_VECTOR_32          0x758BA00CUL
	#define WAKE_VECTOR_64          0x758BA018UL
	</WAKE_VECTOR_INFO>
  <RESET_REGISTER_INFO>
	#define RESET_REGISTER_ADDRESS  0xCF9UL
	#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
	#define RESET_REGISTER_VALUE    0x6U
	</RESET_REGISTER_INFO>
  <PM_INFO>
	#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_EVT_BIT_WIDTH      0x20U
	#define PM1A_EVT_BIT_OFFSET     0x0U
	#define PM1A_EVT_ADDRESS        0x1800UL
	#define PM1A_EVT_ACCESS_SIZE    0x2U
	#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_EVT_BIT_WIDTH      0x0U
	#define PM1B_EVT_BIT_OFFSET     0x0U
	#define PM1B_EVT_ADDRESS        0x0UL
	#define PM1B_EVT_ACCESS_SIZE    0x2U
	#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_CNT_BIT_WIDTH      0x10U
	#define PM1A_CNT_BIT_OFFSET     0x0U
	#define PM1A_CNT_ADDRESS        0x1804UL
	#define PM1A_CNT_ACCESS_SIZE    0x2U
	#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_CNT_BIT_WIDTH      0x0U
	#define PM1B_CNT_BIT_OFFSET     0x0U
	#define PM1B_CNT_ADDRESS        0x0UL
	#define PM1B_CNT_ACCESS_SIZE    0x2U
	</PM_INFO>
  <S3_INFO>
	#define S3_PKG_VAL_PM1A         0x5U
	#define S3_PKG_VAL_PM1B         0U
	#define S3_PKG_RESERVED         0x0U
	</S3_INFO>
  <S5_INFO>
	#define S5_PKG_VAL_PM1A         0x7U
	#define S5_PKG_VAL_PM1B         0U
	#define S5_PKG_RESERVED         0x0U
	</S5_INFO>
  <DRHD_INFO>
	#define DRHD_COUNT              2U

	#define DRHD0_DEV_CNT           0x1U
	#define DRHD0_SEGMENT           0x0U
	#define DRHD0_FLAGS             0x0U
	#define DRHD0_REG_BASE          0xFED90000UL
	#define DRHD0_IGNORE            true
	#define DRHD0_DEVSCOPE0_TYPE    0x1U
	#define DRHD0_DEVSCOPE0_ID      0x0U
	#define DRHD0_DEVSCOPE0_BUS     0x0U
	#define DRHD0_DEVSCOPE0_PATH    0x10U

	#define DRHD1_DEV_CNT           0x2U
	#define DRHD1_SEGMENT           0x0U
	#define DRHD1_FLAGS             0x1U
	#define DRHD1_REG_BASE          0xFED91000UL
	#define DRHD1_IGNORE            false
	#define DRHD1_DEVSCOPE0_TYPE    0x3U
	#define DRHD1_DEVSCOPE0_ID      0x2U
	#define DRHD1_DEVSCOPE0_BUS     0x0U
	#define DRHD1_DEVSCOPE0_PATH    0xf7U
	#define DRHD1_DEVSCOPE1_TYPE    0x4U
	#define DRHD1_DEVSCOPE1_ID      0x0U
	#define DRHD1_DEVSCOPE1_BUS     0x0U
	#define DRHD1_DEVSCOPE1_PATH    0xf6U

	</DRHD_INFO>
  <CPU_BRAND>
	"12th Gen Intel(R) Core(TM) i7-12700E"
	</CPU_BRAND>
  <CX_INFO>
	/* Cx data is not available */
	</CX_INFO>
  <PX_INFO>
	/* Px data is not available */
	</PX_INFO>
  <MMCFG_BASE_INFO>
	/* PCI mmcfg base of MCFG */
	#define DEFAULT_PCI_MMCFG_BASE   0xc0000000UL
	</MMCFG_BASE_INFO>
  <TPM_INFO>
	TPM2
	</TPM_INFO>
  <CLOS_INFO>
	rdt resources supported: L2
	rdt resource clos max: 8
	rdt resource mask max: '0x3ff'
	</CLOS_INFO>
  <IOMEM_INFO>
	00000000-00000fff : Reserved
	00001000-0009dfff : System RAM
	0009e000-0009efff : Reserved
	0009f000-0009ffff : System RAM
	000a0000-000fffff : Reserved
	  000a0000-000bffff : PCI Bus 0000:00
	  000e0000-000e3fff : PCI Bus 0000:00
	  000e4000-000e7fff : PCI Bus 0000:00
	  000e8000-000ebfff : PCI Bus 0000:00
	  000ec000-000effff : PCI Bus 0000:00
	  000f0000-000fffff : System ROM
	00100000-2007ffff : System RAM
	20080000-20080fff : Reserved
	20081000-69167fff : System RAM
	69168000-69168fff : Reserved
	69169000-725bffff : System RAM
	725c0000-756bffff : Reserved
	756c0000-7578efff : ACPI Tables
	7578f000-758bafff : ACPI Non-volatile Storage
	758bb000-75ffefff : Reserved
	75fff000-75ffffff : System RAM
	76000000-79ffffff : Reserved
	7a600000-7a7fffff : Reserved
	7b000000-807fffff : Reserved
	  7c800000-807fffff : Graphics Stolen Memory
	80800000-bfffffff : PCI Bus 0000:00
	  80800000-809fffff : PCI Bus 0000:08
	    80800000-808fffff : 0000:08:00.0
	      80800000-808fffff : igc
	    80900000-80903fff : 0000:08:00.0
	      80900000-80903fff : igc
	  80a00000-80bfffff : PCI Bus 0000:06
	    80a00000-80afffff : 0000:06:00.0
	      80a00000-80afffff : igc
	    80b00000-80b03fff : 0000:06:00.0
	      80b00000-80b03fff : igc
	  80c00000-80dfffff : PCI Bus 0000:05
	    80c00000-80cfffff : 0000:05:00.0
	      80c00000-80cfffff : igc
	    80d00000-80d03fff : 0000:05:00.0
	      80d00000-80d03fff : igc
	  80e00000-80ffffff : PCI Bus 0000:04
	    80e00000-80efffff : 0000:04:00.0
	      80e00000-80efffff : igc
	    80f00000-80f03fff : 0000:04:00.0
	      80f00000-80f03fff : igc
	  81000000-811fffff : PCI Bus 0000:03
	    81000000-810fffff : 0000:03:00.0
	      81000000-810fffff : igc
	    81100000-81103fff : 0000:03:00.0
	      81100000-81103fff : igc
	  81200000-812fffff : PCI Bus 0000:01
	    81200000-81203fff : 0000:01:00.0
	      81200000-81203fff : nvme
	  81300000-81301fff : 0000:00:17.0
	    81300000-81301fff : ahci
	  81302000-813027ff : 0000:00:17.0
	    81302000-813027ff : ahci
	  81303000-813030ff : 0000:00:17.0
	    81303000-813030ff : ahci
	  81304000-81304fff : 0000:00:16.3
	  81305000-81305fff : 0000:00:1f.5
	c0000000-cfffffff : PCI MMCONFIG 0000 [bus 00-ff]
	  c0000000-cfffffff : Reserved
	fe000000-fe010fff : Reserved
	fec00000-fec00fff : Reserved
	  fec00000-fec003ff : IOAPIC 0
	fed00000-fed00fff : Reserved
	  fed00000-fed003ff : HPET 0
	    fed00000-fed003ff : PNP0103:00
	fed20000-fed7ffff : Reserved
	  fed40000-fed44fff : MSFT0101:00
	    fed40000-fed44fff : MSFT0101:00 MSFT0101:00
	fed90000-fed93fff : pnp 00:09
	feda0000-feda0fff : pnp 00:09
	feda1000-feda1fff : pnp 00:09
	fedc0000-fedc7fff : pnp 00:09
	fee00000-fee00fff : Local APIC
	  fee00000-fee00fff : Reserved
	ff000000-ffffffff : Reserved
	100000000-87f7fffff : System RAM
	  1e1000000-1e2404206 : Kernel code
	  1e2600000-1e2da6fff : Kernel rodata
	  1e2e00000-1e314c43f : Kernel data
	  1e334b000-1e39fffff : Kernel bss
	87f800000-87fffffff : RAM buffer
	4000000000-7fffffffff : PCI Bus 0000:00
	  4000000000-400fffffff : 0000:00:02.0
	  4010000000-4016ffffff : 0000:00:02.0
	  4017000000-4017000fff : 0000:00:1e.0
	    4017000000-40170001ff : lpss_dev
	      4017000000-401700001f : serial
	    4017000200-40170002ff : lpss_priv
	    4017000800-4017000fff : idma64.0
	      4017000800-4017000fff : idma64.0 idma64.0
	  4017001000-4017001fff : 0000:00:1e.3
	    4017001000-40170011ff : lpss_dev
	      4017001000-40170011ff : pxa2xx-spi.1 lpss_dev
	    4017001200-40170012ff : lpss_priv
	    4017001800-4017001fff : idma64.1
	      4017001800-4017001fff : idma64.1 idma64.1
	  4020000000-40ffffffff : 0000:00:02.0
	  6000000000-6000ffffff : 0000:00:02.0
	  6001000000-60010fffff : 0000:00:1f.3
	  6001100000-600110ffff : 0000:00:14.0
	    6001100000-600110ffff : xhci-hcd
	  6001110000-6001113fff : 0000:00:1f.3
	    6001110000-6001113fff : ICH HD audio
	  6001114000-6001117fff : 0000:00:14.2
	  6001118000-60011180ff : 0000:00:1f.4
	  600111b000-600111bfff : 0000:00:16.0
	    600111b000-600111bfff : mei_me
	  600111c000-600111cfff : 0000:00:14.2
	</IOMEM_INFO>
  <BLOCK_DEVICE_INFO>
	/dev/nvme0n1p2: TYPE="ext4"
	</BLOCK_DEVICE_INFO>
  <TTYS_INFO>
	seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
	seri:/dev/ttyS1 type:portio base:0x2F8 irq:3
	seri:/dev/ttyS2 type:portio base:0x3E8 irq:7
	seri:/dev/ttyS3 type:portio base:0x2E8 irq:7
	seri:/dev/ttyS4 type:portio base:0x2E0 irq:10
	seri:/dev/ttyS5 type:portio base:0x2F0 irq:10
	seri:/dev/ttyS6 type:portio base:0x30A0 irq:19 bdf:0:22.3
	seri:/dev/ttyS7 type:mmio base:0x4017000000 irq:16 bdf:"00:1e.0"
	</TTYS_INFO>
  <AVAILABLE_IRQ_INFO>
	5, 6, 11, 12, 13, 14, 15
	</AVAILABLE_IRQ_INFO>
  <TOTAL_MEM_INFO>
	32642608 kB
	</TOTAL_MEM_INFO>
  <CPU_PROCESSOR_INFO>
	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
	</CPU_PROCESSOR_INFO>
  <MAX_MSIX_TABLE_NUM>
	9
	</MAX_MSIX_TABLE_NUM>
  <processors>
    <model description="12th Gen Intel(R) Core(TM) i7-12700E">
      <family_id>0x6</family_id>
      <model_id>0x97</model_id>
      <core_type>Core</core_type>
      <native_model_id>0x1</native_model_id>
      <capability id="sse3"/>
      <capability id="pclmulqdq"/>
      <capability id="dtes64"/>
      <capability id="monitor"/>
      <capability id="ds_cpl"/>
      <capability id="vmx"/>
      <capability id="smx"/>
      <capability id="est"/>
      <capability id="tm2"/>
      <capability id="ssse3"/>
      <capability id="sdbg"/>
      <capability id="fma"/>
      <capability id="cmpxchg16b"/>
      <capability id="xtpr"/>
      <capability id="pdcm"/>
      <capability id="pcid"/>
      <capability id="sse4_1"/>
      <capability id="sse4_2"/>
      <capability id="x2apic"/>
      <capability id="movbe"/>
      <capability id="popcnt"/>
      <capability id="tsc_deadline"/>
      <capability id="aes"/>
      <capability id="xsave"/>
      <capability id="avx"/>
      <capability id="f16c"/>
      <capability id="rdrand"/>
      <capability id="fpu"/>
      <capability id="vme"/>
      <capability id="de"/>
      <capability id="pse"/>
      <capability id="tsc"/>
      <capability id="msr"/>
      <capability id="pae"/>
      <capability id="mce"/>
      <capability id="cx8"/>
      <capability id="apic"/>
      <capability id="sep"/>
      <capability id="mtrr"/>
      <capability id="pge"/>
      <capability id="mca"/>
      <capability id="cmov"/>
      <capability id="pat"/>
      <capability id="pse36"/>
      <capability id="clfsh"/>
      <capability id="ds"/>
      <capability id="acpi"/>
      <capability id="mmx"/>
      <capability id="fxsr"/>
      <capability id="sse"/>
      <capability id="sse2"/>
      <capability id="ss"/>
      <capability id="htt"/>
      <capability id="tm"/>
      <capability id="pbe"/>
      <capability id="digital_temperature_sensor_supported"/>
      <capability id="arat_supported"/>
      <capability id="pln_supported"/>
      <capability id="ecmd_supported"/>
      <capability id="package_thermal_management_supported"/>
      <capability id="hwp_supported"/>
      <capability id="hwp_notification"/>
      <capability id="hwp_activity_window"/>
      <capability id="hwp_energy_performance_preference"/>
      <capability id="hwp_package_level_request"/>
      <capability id="hwp_capabilities"/>
      <capability id="hwp_peci_override"/>
      <capability id="flexible_hwp"/>
      <capability id="fast_hwp_request"/>
      <capability id="hw_feedback"/>
      <capability id="ignoring_idle_hwp"/>
      <capability id="thread_director"/>
      <capability id="hardware_coordination_feedback_capability"/>
      <capability id="performance_energy_bias"/>
      <capability id="digital_temperature_sensor_supported"/>
      <capability id="arat_supported"/>
      <capability id="pln_supported"/>
      <capability id="ecmd_supported"/>
      <capability id="package_thermal_management_supported"/>
      <capability id="hwp_supported"/>
      <capability id="hwp_notification"/>
      <capability id="hwp_activity_window"/>
      <capability id="hwp_energy_performance_preference"/>
      <capability id="hwp_package_level_request"/>
      <capability id="hwp_capabilities"/>
      <capability id="hwp_peci_override"/>
      <capability id="flexible_hwp"/>
      <capability id="fast_hwp_request"/>
      <capability id="hw_feedback"/>
      <capability id="ignoring_idle_hwp"/>
      <capability id="thread_director"/>
      <capability id="hardware_coordination_feedback_capability"/>
      <capability id="performance_energy_bias"/>
      <capability id="fsgsbase"/>
      <capability id="ia32_tsc_adjust_msr"/>
      <capability id="bmi1"/>
      <capability id="avx2"/>
      <capability id="fdp_excptn_only"/>
      <capability id="smep"/>
      <capability id="bmi2"/>
      <capability id="erms"/>
      <capability id="invpcid"/>
      <capability id="deprecate_fpu"/>
      <capability id="rdt_a"/>
      <capability id="rdseed"/>
      <capability id="adx"/>
      <capability id="smap"/>
      <capability id="clflushopt"/>
      <capability id="clwb"/>
      <capability id="intel_pt"/>
      <capability id="sha"/>
      <capability id="umip"/>
      <capability id="pku"/>
      <capability id="waitpkg"/>
      <capability id="cet_ss"/>
      <capability id="gfni"/>
      <capability id="vaes"/>
      <capability id="vpclmulqdq"/>
      <capability id="tme_en"/>
      <capability id="rdpid"/>
      <capability id="kl"/>
      <capability id="movdiri"/>
      <capability id="movdiri64b"/>
      <capability id="pks"/>
      <capability id="fast_short_rep_mov"/>
      <capability id="md_clear"/>
      <capability id="hybrid"/>
      <capability id="pconfig"/>
      <capability id="cet_ibt"/>
      <capability id="ibrs_ibpb"/>
      <capability id="stibp"/>
      <capability id="l1d_flush"/>
      <capability id="ia32_arch_capabilities"/>
      <capability id="ia32_core_capabilities"/>
      <capability id="ssbd"/>
      <capability id="lahf_sahf_64"/>
      <capability id="lzcnt"/>
      <capability id="prefetchw"/>
      <capability id="syscall_sysret_64"/>
      <capability id="execute_disable"/>
      <capability id="gbyte_pages"/>
      <capability id="rdtscp_ia32_tsc_aux"/>
      <capability id="intel_64"/>
      <capability id="invariant_tsc"/>
      <capability id="fast_string"/>
      <capability id="vmx_pinbased_ctls_irq_exit"/>
      <capability id="ept"/>
      <capability id="apicv"/>
      <capability id="vmx_procbased_ctls_tsc_off"/>
      <capability id="vmx_procbased_ctls_tpr_shadow"/>
      <capability id="vmx_procbased_ctls_io_bitmap"/>
      <capability id="vmx_procbased_ctls_msr_bitmap"/>
      <capability id="vmx_procbased_ctls_hlt"/>
      <capability id="vmx_procbased_ctls_secondary"/>
      <capability id="vmx_exit_ctls_ack_irq"/>
      <capability id="vmx_exit_ctls_save_pat"/>
      <capability id="vmx_exit_ctls_load_pat"/>
      <capability id="vmx_exit_ctls_host_addr64"/>
      <capability id="vmx_entry_ctls_load_pat"/>
      <capability id="vmx_entry_ctls_ia32e_mode"/>
      <capability id="stores_lma_on_exit"/>
      <capability id="vmx_procbased_ctls2_vapic"/>
      <capability id="vmx_procbased_ctls2_ept"/>
      <capability id="vmx_procbased_ctls2_vpid"/>
      <capability id="vmx_procbased_ctls2_rdtscp"/>
      <capability id="vmx_procbased_ctls2_unrestrict"/>
      <capability id="invept"/>
      <capability id="invvpid"/>
      <capability id="ept_2mb_page"/>
      <capability id="vmx_ept_1gb_page"/>
      <attribute id="cpuid_level">0x20</attribute>
      <attribute id="physical_address_bits">46</attribute>
      <attribute id="linear_address_bits">48</attribute>
      <attribute id="max_ratio_1core">48</attribute>
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    <model description="12th Gen Intel(R) Core(TM) i7-12700E">
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      <native_model_id>0x1</native_model_id>
      <capability id="sse3"/>
      <capability id="pclmulqdq"/>
      <capability id="dtes64"/>
      <capability id="monitor"/>
      <capability id="ds_cpl"/>
      <capability id="vmx"/>
      <capability id="smx"/>
      <capability id="est"/>
      <capability id="tm2"/>
      <capability id="ssse3"/>
      <capability id="sdbg"/>
      <capability id="fma"/>
      <capability id="cmpxchg16b"/>
      <capability id="xtpr"/>
      <capability id="pdcm"/>
      <capability id="pcid"/>
      <capability id="sse4_1"/>
      <capability id="sse4_2"/>
      <capability id="x2apic"/>
      <capability id="movbe"/>
      <capability id="popcnt"/>
      <capability id="tsc_deadline"/>
      <capability id="aes"/>
      <capability id="xsave"/>
      <capability id="avx"/>
      <capability id="f16c"/>
      <capability id="rdrand"/>
      <capability id="fpu"/>
      <capability id="vme"/>
      <capability id="de"/>
      <capability id="pse"/>
      <capability id="tsc"/>
      <capability id="msr"/>
      <capability id="pae"/>
      <capability id="mce"/>
      <capability id="cx8"/>
      <capability id="apic"/>
      <capability id="sep"/>
      <capability id="mtrr"/>
      <capability id="pge"/>
      <capability id="mca"/>
      <capability id="cmov"/>
      <capability id="pat"/>
      <capability id="pse36"/>
      <capability id="clfsh"/>
      <capability id="ds"/>
      <capability id="acpi"/>
      <capability id="mmx"/>
      <capability id="fxsr"/>
      <capability id="sse"/>
      <capability id="sse2"/>
      <capability id="ss"/>
      <capability id="htt"/>
      <capability id="tm"/>
      <capability id="pbe"/>
      <capability id="digital_temperature_sensor_supported"/>
      <capability id="arat_supported"/>
      <capability id="pln_supported"/>
      <capability id="ecmd_supported"/>
      <capability id="package_thermal_management_supported"/>
      <capability id="hwp_supported"/>
      <capability id="hwp_notification"/>
      <capability id="hwp_activity_window"/>
      <capability id="hwp_energy_performance_preference"/>
      <capability id="hwp_package_level_request"/>
      <capability id="hwp_capabilities"/>
      <capability id="hwp_peci_override"/>
      <capability id="flexible_hwp"/>
      <capability id="fast_hwp_request"/>
      <capability id="hw_feedback"/>
      <capability id="ignoring_idle_hwp"/>
      <capability id="thread_director"/>
      <capability id="hardware_coordination_feedback_capability"/>
      <capability id="performance_energy_bias"/>
      <capability id="digital_temperature_sensor_supported"/>
      <capability id="arat_supported"/>
      <capability id="pln_supported"/>
      <capability id="ecmd_supported"/>
      <capability id="package_thermal_management_supported"/>
      <capability id="hwp_supported"/>
      <capability id="hwp_notification"/>
      <capability id="hwp_activity_window"/>
      <capability id="hwp_energy_performance_preference"/>
      <capability id="hwp_package_level_request"/>
      <capability id="hwp_capabilities"/>
      <capability id="hwp_peci_override"/>
      <capability id="flexible_hwp"/>
      <capability id="fast_hwp_request"/>
      <capability id="hw_feedback"/>
      <capability id="ignoring_idle_hwp"/>
      <capability id="thread_director"/>
      <capability id="hardware_coordination_feedback_capability"/>
      <capability id="performance_energy_bias"/>
      <capability id="fsgsbase"/>
      <capability id="ia32_tsc_adjust_msr"/>
      <capability id="bmi1"/>
      <capability id="avx2"/>
      <capability id="fdp_excptn_only"/>
      <capability id="smep"/>
      <capability id="bmi2"/>
      <capability id="erms"/>
      <capability id="invpcid"/>
      <capability id="deprecate_fpu"/>
      <capability id="rdt_a"/>
      <capability id="rdseed"/>
      <capability id="adx"/>
      <capability id="smap"/>
      <capability id="clflushopt"/>
      <capability id="clwb"/>
      <capability id="intel_pt"/>
      <capability id="sha"/>
      <capability id="umip"/>
      <capability id="pku"/>
      <capability id="waitpkg"/>
      <capability id="cet_ss"/>
      <capability id="gfni"/>
      <capability id="vaes"/>
      <capability id="vpclmulqdq"/>
      <capability id="tme_en"/>
      <capability id="rdpid"/>
      <capability id="kl"/>
      <capability id="movdiri"/>
      <capability id="movdiri64b"/>
      <capability id="pks"/>
      <capability id="fast_short_rep_mov"/>
      <capability id="md_clear"/>
      <capability id="hybrid"/>
      <capability id="pconfig"/>
      <capability id="cet_ibt"/>
      <capability id="ibrs_ibpb"/>
      <capability id="stibp"/>
      <capability id="l1d_flush"/>
      <capability id="ia32_arch_capabilities"/>
      <capability id="ia32_core_capabilities"/>
      <capability id="ssbd"/>
      <capability id="lahf_sahf_64"/>
      <capability id="lzcnt"/>
      <capability id="prefetchw"/>
      <capability id="syscall_sysret_64"/>
      <capability id="execute_disable"/>
      <capability id="gbyte_pages"/>
      <capability id="rdtscp_ia32_tsc_aux"/>
      <capability id="intel_64"/>
      <capability id="invariant_tsc"/>
      <capability id="fast_string"/>
      <capability id="vmx_pinbased_ctls_irq_exit"/>
      <capability id="ept"/>
      <capability id="apicv"/>
      <capability id="vmx_procbased_ctls_tsc_off"/>
      <capability id="vmx_procbased_ctls_tpr_shadow"/>
      <capability id="vmx_procbased_ctls_io_bitmap"/>
      <capability id="vmx_procbased_ctls_msr_bitmap"/>
      <capability id="vmx_procbased_ctls_hlt"/>
      <capability id="vmx_procbased_ctls_secondary"/>
      <capability id="vmx_exit_ctls_ack_irq"/>
      <capability id="vmx_exit_ctls_save_pat"/>
      <capability id="vmx_exit_ctls_load_pat"/>
      <capability id="vmx_exit_ctls_host_addr64"/>
      <capability id="vmx_entry_ctls_load_pat"/>
      <capability id="vmx_entry_ctls_ia32e_mode"/>
      <capability id="stores_lma_on_exit"/>
      <capability id="vmx_procbased_ctls2_vapic"/>
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      <capability id="vmx_procbased_ctls2_rdtscp"/>
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      <capability id="invept"/>
      <capability id="invvpid"/>
      <capability id="ept_2mb_page"/>
      <capability id="vmx_ept_1gb_page"/>
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          <core_type>Core</core_type>
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          <core_type>Core</core_type>
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          <core_type>Core</core_type>
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          <core_type>Atom</core_type>
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          <stepping_id>0x2</stepping_id>
          <core_type>Atom</core_type>
          <native_model_id>0x1</native_model_id>
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      </core>
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          <stepping_id>0x2</stepping_id>
          <core_type>Atom</core_type>
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          <lowest_performance_lvl>1</lowest_performance_lvl>
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      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x28</processor>
      </processors>
    </cache>
    <cache level="1" id="0x14" type="2">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x28</processor>
      </processors>
    </cache>
    <cache level="1" id="0x18" type="1">
      <cache_size>49152</cache_size>
      <line_size>64</line_size>
      <ways>12</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x30</processor>
      </processors>
    </cache>
    <cache level="1" id="0x18" type="2">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x30</processor>
      </processors>
    </cache>
    <cache level="1" id="0x1c" type="1">
      <cache_size>49152</cache_size>
      <line_size>64</line_size>
      <ways>12</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x38</processor>
      </processors>
    </cache>
    <cache level="1" id="0x1c" type="2">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x38</processor>
      </processors>
    </cache>
    <cache level="1" id="0x24" type="1">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x48</processor>
      </processors>
    </cache>
    <cache level="1" id="0x24" type="2">
      <cache_size>65536</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>128</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x48</processor>
      </processors>
    </cache>
    <cache level="1" id="0x25" type="1">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x4a</processor>
      </processors>
    </cache>
    <cache level="1" id="0x25" type="2">
      <cache_size>65536</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>128</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x4a</processor>
      </processors>
    </cache>
    <cache level="1" id="0x26" type="1">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x4c</processor>
      </processors>
    </cache>
    <cache level="1" id="0x26" type="2">
      <cache_size>65536</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>128</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x4c</processor>
      </processors>
    </cache>
    <cache level="1" id="0x27" type="1">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x4e</processor>
      </processors>
    </cache>
    <cache level="1" id="0x27" type="2">
      <cache_size>65536</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>128</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x4e</processor>
      </processors>
    </cache>
    <cache level="2" id="0x0" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x0</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x1" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x8</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x2" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x10</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x3" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x18</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x4" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x20</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x5" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x28</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x6" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x30</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x7" type="3">
      <cache_size>1310720</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x38</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>8</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="2" id="0x9" type="3">
      <cache_size>2097152</cache_size>
      <line_size>64</line_size>
      <ways>16</ways>
      <sets>2048</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x48</processor>
        <processor>0x4a</processor>
        <processor>0x4c</processor>
        <processor>0x4e</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>16</capacity_mask_length>
        <clos_number>16</clos_number>
      </capability>
      <capability id="CDP"/>
      <parameter id="IA Waymask">
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
        <waymask>0xffff</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>17</native>
      </parameter>
    </cache>
    <cache level="3" id="0x0" type="3">
      <cache_size>26214400</cache_size>
      <line_size>64</line_size>
      <ways>10</ways>
      <sets>40960</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>1</complex_cache_indexing>
      <processors>
        <processor>0x0</processor>
        <processor>0x8</processor>
        <processor>0x10</processor>
        <processor>0x18</processor>
        <processor>0x20</processor>
        <processor>0x28</processor>
        <processor>0x30</processor>
        <processor>0x38</processor>
        <processor>0x48</processor>
        <processor>0x4a</processor>
        <processor>0x4c</processor>
        <processor>0x4e</processor>
      </processors>
      <capability id="CAT">
        <capacity_mask_length>10</capacity_mask_length>
        <clos_number>16</clos_number>
      </capability>
      <parameter id="IA Waymask">
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
        <waymask>0x3ff</waymask>
      </parameter>
      <parameter id="GT Waymask">
        <waymask>0x1</waymask>
      </parameter>
      <parameter id="Worst Case Access Latency">
        <native>139</native>
      </parameter>
    </cache>
    <parameter id="RTCT Version">
      <major>2</major>
      <minor>0</minor>
    </parameter>
    <parameter id="RTCD Version">
      <major>2</major>
      <minor>0</minor>
    </parameter>
    <parameter id="Total IA L2 CLOS">8</parameter>
    <parameter id="Total IA L3 CLOS">16</parameter>
    <parameter id="Total IA L2 Instances">10</parameter>
    <parameter id="Total IA L2 Instances">1</parameter>
    <parameter id="Total GT CLOS">1</parameter>
    <parameter id="Total WRC CLOS">0</parameter>
  </caches>
  <memory>
    <range start="0x0000000000000000" end="0x000000000009dfff" size="647168"/>
    <range start="0x000000000009f000" end="0x000000000009ffff" size="4096"/>
    <range start="0x0000000000100000" end="0x000000002007ffff" size="536346624"/>
    <range start="0x0000000020081000" end="0x00000000725bffff" size="1381232640"/>
    <range start="0x0000000075fff000" end="0x0000000075ffffff" size="4096"/>
    <range start="0x0000000100000000" end="0x000000087f7fffff" size="32203866112"/>
    <range id="TCC Error Log" start="0x0000000020080000" end="0x00000000200801e7" size="488"/>
  </memory>
  <ioapics>
    <ioapic id="0x2">
      <address>0xfec00000</address>
      <gsi_base>0x0</gsi_base>
      <gsi_number>120</gsi_number>
    </ioapic>
  </ioapics>
  <devices>
    <parameter id="Maximum TCC Streams">8</parameter>
    <parameter id="Maximum TCC Registers">550</parameter>
    <bus type="pci" address="0x0" id="0x4668" description="Host bridge: Intel Corporation 12th Gen Core Processor Host Bridge/DRAM Registers">
      <vendor>0x8086</vendor>
      <identifier>0x4668</identifier>
      <subsystem_vendor>0x1849</subsystem_vendor>
      <subsystem_identifier>0x4668</subsystem_identifier>
      <class>0x060000</class>
      <resource type="memory" min="0xa0000" max="0xbffff" len="0x20000"/>
      <resource type="memory" min="0xe0000" max="0xe3fff" len="0x4000"/>
      <resource type="memory" min="0xe4000" max="0xe7fff" len="0x4000"/>
      <resource type="memory" min="0xe8000" max="0xebfff" len="0x4000"/>
      <resource type="memory" min="0xec000" max="0xeffff" len="0x4000"/>
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        <capability id="Power Management"/>
        <capability id="Vendor-Specific"/>
        <capability id="MSI">
          <count>1</count>
          <capability id="64-bit address"/>
        </capability>
      </device>
      <device address="0x1f0004" id="0x7aa3" description="00:1f.4 SMBus: Intel Corporation Alder Lake-S PCH SMBus Controller">
        <vendor>0x8086</vendor>
        <identifier>0x7aa3</identifier>
        <subsystem_vendor>0x1849</subsystem_vendor>
        <subsystem_identifier>0x7aa3</subsystem_identifier>
        <class>0x0c0500</class>
        <resource type="interrupt_pin" pin="INTC#"/>
        <resource type="io_port" min="0xefa0" max="0xefbf" len="0x20" id="bar4"/>
        <resource type="memory" min="0x6001118000" max="0x60011180ff" len="0x100" id="bar0" width="64" prefetchable="0"/>
      </device>
      <device address="0x1f0005" id="0x7aa4" description="00:1f.5 Serial bus controller: Intel Corporation Alder Lake-S PCH SPI Controller">
        <vendor>0x8086</vendor>
        <identifier>0x7aa4</identifier>
        <subsystem_vendor>0x1849</subsystem_vendor>
        <subsystem_identifier>0x7aa4</subsystem_identifier>
        <class>0x0c8000</class>
        <resource type="memory" min="0x81305000" max="0x81305fff" len="0x1000" id="bar0" width="32" prefetchable="0"/>
      </device>
    </bus>
  </devices>
  <device-classes>
    <inputs>
      <input>
        <name>Sleep Button</name>
        <phys>PNP0C0E/button/input0</phys>
      </input>
      <input>
        <name>Power Button</name>
        <phys>PNP0C0C/button/input0</phys>
      </input>
      <input>
        <name>Power Button</name>
        <phys>LNXPWRBN/button/input0</phys>
      </input>
      <input>
        <name>Video Bus</name>
        <phys>LNXVIDEO/video/input0</phys>
      </input>
      <input>
        <name>USB usb keyboard</name>
        <phys>usb-0000:00:14.0-8/input0</phys>
      </input>
      <input>
        <name>USB usb keyboard Consumer Control</name>
        <phys>usb-0000:00:14.0-8/input1</phys>
      </input>
      <input>
        <name>USB usb keyboard System Control</name>
        <phys>usb-0000:00:14.0-8/input1</phys>
      </input>
      <input>
        <name>HDA Intel PCH Front Mic</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH Rear Mic</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH Line Out</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH Front Headphone</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=3</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=7</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=8</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=9</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=10</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=11</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=12</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=13</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=14</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=15</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=16</name>
        <phys>ALSA</phys>
      </input>
      <input>
        <name>HDA Intel PCH HDMI/DP,pcm=17</name>
        <phys>ALSA</phys>
      </input>
    </inputs>
    <ttys>
      <serial>
        <dev_path>/dev/ttyS0</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS1</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS2</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS3</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS4</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS5</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS6</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS7</dev_path>
        <type>4</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS8</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS9</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS10</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS11</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS12</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS13</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS14</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS15</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS16</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS17</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS18</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS19</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS20</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS21</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS22</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS23</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS24</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS25</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS26</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS27</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS28</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS29</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS30</dev_path>
        <type>0</type>
      </serial>
      <serial>
        <dev_path>/dev/ttyS31</dev_path>
        <type>0</type>
      </serial>
    </ttys>
  </device-classes>
</acrn-config>
