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acrn-config: fix build issue while CDP_ENABLED=y

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Fix build issue while CDP_ENABLED=y for EHL-CRB-B.

Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Wei Liu 2020-08-14 20:15:46 +08:00 committed by wenlingz
parent 23d9c13c41
commit 01362c3cd1
4 changed files with 9 additions and 15 deletions
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12
misc/acrn-config/board_config/board_c.py
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@ -139,6 +139,8 @@ def gen_rdt_res(config):
cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK") cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK")
mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY") mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY")
# TODO: Since use the MAX_PLATFORM_CLOS_NUM for L2/L3/MBA, so use the minimal number of them
common_clos_max = min(len(cat_mask_list), len(mba_delay_list))
if common_clos_max > MSR_IA32_L2_MASK_END - MSR_IA32_L2_MASK_BASE or\ if common_clos_max > MSR_IA32_L2_MASK_END - MSR_IA32_L2_MASK_BASE or\
common_clos_max > MSR_IA32_L3_MASK_END - MSR_IA32_L3_MASK_BASE: common_clos_max > MSR_IA32_L3_MASK_END - MSR_IA32_L3_MASK_BASE:
@ -149,27 +151,27 @@ def gen_rdt_res(config):
if len(rdt_resources) == 0 or common_clos_max == 0: if len(rdt_resources) == 0 or common_clos_max == 0:
print("struct platform_clos_info platform_{0}_clos_array[MAX_PLATFORM_CLOS_NUM];".format("l2"), file=config) print("struct platform_clos_info platform_{0}_clos_array[MAX_PLATFORM_CLOS_NUM];".format("l2"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[MAX_PLATFORM_CLOS_NUM];".format("l3"), file=config) print("struct platform_clos_info platform_{0}_clos_array[MAX_PLATFORM_CLOS_NUM];".format("l3"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];".format("mba"), file=config) print("struct platform_clos_info platform_{0}_clos_array[MAX_PLATFORM_CLOS_NUM];".format("mba"), file=config)
else: else:
for idx, rdt_res in enumerate(rdt_resources): for idx, rdt_res in enumerate(rdt_resources):
if rdt_res == "L2": if rdt_res == "L2":
rdt_res_str = "l2" rdt_res_str = "l2"
print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str, print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
"MAX_CACHE_CLOS_NUM_ENTRIES"), file=config) "MAX_PLATFORM_CLOS_NUM"), file=config)
populate_clos_mask_msr(rdt_res, cat_mask_list, config) populate_clos_mask_msr(rdt_res, cat_mask_list, config)
print("};\n", file=config) print("};\n", file=config)
res_present[RDT.L2.value] = 1 res_present[RDT.L2.value] = 1
elif rdt_res == "L3": elif rdt_res == "L3":
rdt_res_str = "l3" rdt_res_str = "l3"
print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str, print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
"MAX_CACHE_CLOS_NUM_ENTRIES"), file=config) "MAX_PLATFORM_CLOS_NUM"), file=config)
populate_clos_mask_msr(rdt_res, cat_mask_list, config) populate_clos_mask_msr(rdt_res, cat_mask_list, config)
print("};\n", file=config) print("};\n", file=config)
res_present[RDT.L3.value] = 1 res_present[RDT.L3.value] = 1
elif rdt_res == "MBA": elif rdt_res == "MBA":
rdt_res_str = "mba" rdt_res_str = "mba"
print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str, print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
"MAX_MBA_CLOS_NUM_ENTRIES"), file=config) "MAX_PLATFORM_CLOS_NUM"), file=config)
err_dic = populate_mba_delay_mask(rdt_res, mba_delay_list, config) err_dic = populate_mba_delay_mask(rdt_res, mba_delay_list, config)
print("};\n", file=config) print("};\n", file=config)
res_present[RDT.MBA.value] = 1 res_present[RDT.MBA.value] = 1
@ -182,7 +184,7 @@ def gen_rdt_res(config):
if res_present[RDT.L3.value] == 0: if res_present[RDT.L3.value] == 0:
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l3", "MAX_PLATFORM_CLOS_NUM"), file=config) print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l3", "MAX_PLATFORM_CLOS_NUM"), file=config)
if res_present[RDT.MBA.value] == 0: if res_present[RDT.MBA.value] == 0:
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("mba", "MAX_MBA_CLOS_NUM_ENTRIES"), file=config) print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("mba", "MAX_PLATFORM_CLOS_NUM"), file=config)
print("#endif", file=config) print("#endif", file=config)

1
misc/acrn-config/board_config/board_info_h.py
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@ -82,7 +82,6 @@ def generate_file(config):
# define CONFIG_MAX_PCPCU_NUM # define CONFIG_MAX_PCPCU_NUM
print("#define MAX_PCPU_NUM\t\t\t{}U".format(max_cpu_num), file=config) print("#define MAX_PCPU_NUM\t\t\t{}U".format(max_cpu_num), file=config)
print("#define MAX_PLATFORM_CLOS_NUM\t\t{}U".format(common_clos_max), file=config) print("#define MAX_PLATFORM_CLOS_NUM\t\t{}U".format(common_clos_max), file=config)
print("#define MAX_MBA_CLOS_NUM_ENTRIES\t{}U".format(max_mba_clos_entries), file=config)
# define MAX_VMSIX_ON_MSI_PDEVS_NUM # define MAX_VMSIX_ON_MSI_PDEVS_NUM
gen_known_caps_pci_head(config) gen_known_caps_pci_head(config)

7
misc/acrn-config/board_config/misc_cfg_h.py
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@ -220,13 +220,6 @@ def generate_file(config):
print("", file=config) print("", file=config)
if board_cfg_lib.is_rdt_supported(): if board_cfg_lib.is_rdt_supported():
print("", file=config)
common_clos_max = board_cfg_lib.get_common_clos_max()
max_cache_clos_entries = common_clos_max
if board_cfg_lib.is_cdp_enabled():
max_cache_clos_entries = 2 * common_clos_max
print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries), file=config)
(rdt_resources, rdt_res_clos_max, _) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE) (rdt_resources, rdt_res_clos_max, _) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK") cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK")
mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY") mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY")

4
misc/acrn-config/library/hv_cfg_lib.py
View File

@ -182,7 +182,7 @@ def cat_max_mask_check(cat_mask_list, feature, cat_str, max_mask_str):
cat_max_mask_settings_len = len(cat_mask_list) cat_max_mask_settings_len = len(cat_mask_list)
if clos_max_set_entry != cat_max_mask_settings_len: if clos_max_set_entry != cat_max_mask_settings_len:
key = 'hv,{},{},{}'.format(feature, cat_str, max_mask_str) key = 'hv,{},{},{}'.format(feature, cat_str, max_mask_str)
ERR_LIST[key] = "Number of Cache mask entries should be equal to MAX_CACHE_CLOS_NUM_ENTRIES={}".format(clos_max_set_entry) ERR_LIST[key] = "Number of Cache mask entries should be equal to MAX_PLATFORM_CLOS_NUM={}".format(clos_max_set_entry)
return return
clos_max_mask_str = clos_max_mask_list[0].strip('"').strip("'") clos_max_mask_str = clos_max_mask_list[0].strip('"').strip("'")
@ -212,7 +212,7 @@ def mba_delay_check(mba_delay_list, feature, mba_str, max_mask_str):
mba_delay_settings_len = len(mba_delay_list) mba_delay_settings_len = len(mba_delay_list)
if clos_max != mba_delay_settings_len: if clos_max != mba_delay_settings_len:
key = 'hv,{},{},{}'.format(feature, mba_str, max_mask_str) key = 'hv,{},{},{}'.format(feature, mba_str, max_mask_str)
ERR_LIST[key] = "Number of MBA delay entries should be equal to MAX_MBA_CLOS_NUM_ENTRIES={}".format(clos_max) ERR_LIST[key] = "Number of MBA delay entries should be equal to MAX_PLATFORM_CLOS_NUM={}".format(clos_max)
return return
mba_idx = res_info.index("MBA") mba_idx = res_info.index("MBA")