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hv: pass pointer to functions

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Pass intr_src and dmar_ir_entry irte as pointers to dmar_assign_irte(),
which fixes the "Attempt to change parameter passed by value" MISRA C violation.

A few coding style fixes

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
dongshen 2020-03-18 15:15:54 -07:00 committed by wenlingz
parent 0f3c876a91
commit 016c1a5073
3 changed files with 40 additions and 36 deletions
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18
hypervisor/arch/x86/guest/assign.c
View File

@ -77,7 +77,7 @@ static void ptirq_free_irte(const struct ptirq_remapping_info *entry)
intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(entry->allocated_pirq);
}
dmar_free_irte(intr_src, (uint16_t)entry->allocated_pirq);
dmar_free_irte(&intr_src, (uint16_t)entry->allocated_pirq);
}
static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *info,
@ -117,7 +117,7 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *
intr_src.is_msi = true;
intr_src.src.msi.value = entry->phys_sid.msi_id.bdf;
ret = dmar_assign_irte(intr_src, irte, (uint16_t)entry->allocated_pirq);
ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)entry->allocated_pirq);
if (ret == 0) {
/*
@ -213,7 +213,7 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
intr_src.is_msi = false;
intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(phys_irq);
ret = dmar_assign_irte(intr_src, irte, (uint16_t)phys_irq);
ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)phys_irq);
if (ret == 0) {
ir_index.index = (uint16_t)phys_irq;
@ -299,7 +299,8 @@ static struct ptirq_remapping_info *add_msix_remapping(struct acrn_vm *vm,
}
} else {
/* The mapping has already been added to the VM. No action
* required. */
* required.
*/
}
dev_dbg(DBG_LEVEL_IRQ, "VM%d MSIX add vector mapping vbdf%x:pbdf%x idx=%d",
@ -325,7 +326,7 @@ remove_msix_remapping(const struct acrn_vm *vm, uint16_t virt_bdf, uint32_t entr
intr_src.is_msi = true;
intr_src.src.msi.value = entry->phys_sid.msi_id.bdf;
dmar_free_irte(intr_src, (uint16_t)entry->allocated_pirq);
dmar_free_irte(&intr_src, (uint16_t)entry->allocated_pirq);
dev_dbg(DBG_LEVEL_IRQ,
"VM%d MSIX remove vector mapping vbdf-pbdf:0x%x-0x%x idx=%d",
@ -380,7 +381,8 @@ static struct ptirq_remapping_info *add_intx_remapping(struct acrn_vm *vm, uint3
}
} else {
/* The mapping has already been added to the VM. No action
* required. */
* required.
*/
}
@ -415,7 +417,7 @@ static void remove_intx_remapping(const struct acrn_vm *vm, uint32_t virt_gsi, e
intr_src.is_msi = false;
intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(phys_irq);
dmar_free_irte(intr_src, (uint16_t)phys_irq);
dmar_free_irte(&intr_src, (uint16_t)phys_irq);
dev_dbg(DBG_LEVEL_IRQ,
"deactive %s intx entry:pgsi=%d, pirq=%d ",
(vgsi_ctlr == INTX_CTLR_PIC) ? "vPIC" : "vIOAPIC",
@ -432,6 +434,7 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
const struct ptirq_remapping_info *entry)
{
const union source_id *virt_sid = &entry->virt_sid;
switch (virt_sid->intx_id.ctlr) {
case INTX_CTLR_IOAPIC:
{
@ -597,6 +600,7 @@ int32_t ptirq_prepare_msix_remap(struct acrn_vm *vm, uint16_t virt_bdf, uint16_t
/* build physical config MSI, update to info->pmsi_xxx */
if (is_lapic_pt_configured(vm)) {
enum vm_vlapic_state vlapic_state = check_vm_vlapic_state(vm);
if (vlapic_state == VM_VLAPIC_X2APIC) {
/*
* All the vCPUs are in x2APIC mode and LAPIC is Pass-through

54
hypervisor/arch/x86/vtd.c
View File

@ -152,13 +152,13 @@ struct intr_remap_table {
struct page tables[CONFIG_MAX_IR_ENTRIES/DMAR_NUM_IR_ENTRIES_PER_PAGE];
};
static inline uint8_t* get_root_table(uint32_t dmar_index)
static inline uint8_t *get_root_table(uint32_t dmar_index)
{
static struct page root_tables[CONFIG_MAX_IOMMU_NUM] __aligned(PAGE_SIZE);
return root_tables[dmar_index].contents;
}
static inline uint8_t* get_ctx_table(uint32_t dmar_index, uint8_t bus_no)
static inline uint8_t *get_ctx_table(uint32_t dmar_index, uint8_t bus_no)
{
static struct context_table ctx_tables[CONFIG_MAX_IOMMU_NUM] __aligned(PAGE_SIZE);
return ctx_tables[dmar_index].buses[bus_no].contents;
@ -945,7 +945,7 @@ static void dmar_setup_interrupt(struct dmar_drhd_rt *dmar_unit)
}
spinlock_release(&(dmar_unit->lock));
/* the panic will only happen before any VM starts running */
if (retval < 0 ) {
if (retval < 0) {
panic("dmar[%d] fail to setup interrupt", dmar_unit->index);
}
@ -1249,7 +1249,7 @@ struct iommu_domain *create_iommu_domain(uint16_t vm_id, uint64_t translation_ta
if (translation_table == 0UL) {
pr_err("translation table is NULL");
domain = NULL;
domain = NULL;
} else {
/*
* A hypercall is called to create an iommu domain for a valid VM,
@ -1371,7 +1371,7 @@ int32_t init_iommu(void)
return ret;
}
int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte, uint16_t index)
int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte, uint16_t index)
{
struct dmar_drhd_rt *dmar_unit;
union dmar_ir_entry *ir_table, *ir_entry;
@ -1379,13 +1379,13 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
uint64_t trigger_mode;
int32_t ret = 0;
if (intr_src.is_msi) {
dmar_unit = device_to_dmaru((uint8_t)intr_src.src.msi.bits.b, intr_src.src.msi.fields.devfun);
sid.value = intr_src.src.msi.value;
if (intr_src->is_msi) {
dmar_unit = device_to_dmaru((uint8_t)intr_src->src.msi.bits.b, intr_src->src.msi.fields.devfun);
sid.value = (uint16_t)(intr_src->src.msi.value);
trigger_mode = 0x0UL;
} else {
dmar_unit = ioapic_to_dmaru(intr_src.src.ioapic_id, &sid);
trigger_mode = irte.bits.trigger_mode;
dmar_unit = ioapic_to_dmaru(intr_src->src.ioapic_id, &sid);
trigger_mode = irte->bits.trigger_mode;
}
if (dmar_unit == NULL) {
@ -1399,17 +1399,17 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
ret = -EINVAL;
} else {
dmar_enable_intr_remapping(dmar_unit);
irte.bits.svt = 0x1UL;
irte.bits.sq = 0x0UL;
irte.bits.sid = sid.value;
irte.bits.present = 0x1UL;
irte.bits.mode = 0x0UL;
irte.bits.trigger_mode = trigger_mode;
irte.bits.fpd = 0x0UL;
irte->bits.svt = 0x1UL;
irte->bits.sq = 0x0UL;
irte->bits.sid = sid.value;
irte->bits.present = 0x1UL;
irte->bits.mode = 0x0UL;
irte->bits.trigger_mode = trigger_mode;
irte->bits.fpd = 0x0UL;
ir_table = (union dmar_ir_entry *)hpa2hva(dmar_unit->ir_table_addr);
ir_entry = ir_table + index;
ir_entry->entry.hi_64 = irte.entry.hi_64;
ir_entry->entry.lo_64 = irte.entry.lo_64;
ir_entry->entry.hi_64 = irte->entry.hi_64;
ir_entry->entry.lo_64 = irte->entry.lo_64;
iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
dmar_invalid_iec(dmar_unit, index, 0U, false);
@ -1417,24 +1417,24 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
return ret;
}
void dmar_free_irte(struct intr_source intr_src, uint16_t index)
void dmar_free_irte(const struct intr_source *intr_src, uint16_t index)
{
struct dmar_drhd_rt *dmar_unit;
union dmar_ir_entry *ir_table, *ir_entry;
union pci_bdf sid;
if (intr_src.is_msi) {
dmar_unit = device_to_dmaru((uint8_t)intr_src.src.msi.bits.b, intr_src.src.msi.fields.devfun);
if (intr_src->is_msi) {
dmar_unit = device_to_dmaru((uint8_t)intr_src->src.msi.bits.b, intr_src->src.msi.fields.devfun);
} else {
dmar_unit = ioapic_to_dmaru(intr_src.src.ioapic_id, &sid);
dmar_unit = ioapic_to_dmaru(intr_src->src.ioapic_id, &sid);
}
if (dmar_unit == NULL) {
pr_err("no dmar unit found for device: %x:%x.%x", intr_src.src.msi.bits.b,
intr_src.src.msi.bits.d, intr_src.src.msi.bits.f);
pr_err("no dmar unit found for device: %x:%x.%x", intr_src->src.msi.bits.b,
intr_src->src.msi.bits.d, intr_src->src.msi.bits.f);
} else if (dmar_unit->drhd->ignore) {
dev_dbg(DBG_LEVEL_IOMMU, "device is ignored :0x%x:%x.%x", intr_src.src.msi.bits.b,
intr_src.src.msi.bits.d, intr_src.src.msi.bits.f);
dev_dbg(DBG_LEVEL_IOMMU, "device is ignored :0x%x:%x.%x", intr_src->src.msi.bits.b,
intr_src->src.msi.bits.d, intr_src->src.msi.bits.f);
} else if (dmar_unit->ir_table_addr == 0UL) {
pr_err("IR table is not set for dmar unit");
} else {

4
hypervisor/include/arch/x86/vtd.h
View File

@ -668,7 +668,7 @@ bool iommu_snoop_supported(const struct iommu_domain *iommu);
* @retval 0 otherwise
*
*/
int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte, uint16_t index);
int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte, uint16_t index);
/**
* @brief Free RTE for Interrupt Remapping Table.
@ -677,7 +677,7 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
* @param[in] index into Interrupt Remapping Table
*
*/
void dmar_free_irte(struct intr_source intr_src, uint16_t index);
void dmar_free_irte(const struct intr_source *intr_src, uint16_t index);
/**
* @brief Flash cacheline(s) for a specific address with specific size.