From 055153bf3e7f851ce99e5a431d01e04ea30c4ef4 Mon Sep 17 00:00:00 2001
From: Xiangyang Wu <xiangyang.wu@intel.com>
Date: Fri, 13 Jul 2018 16:27:30 +0800
Subject: [PATCH] HV:treewide:Replace HOST_GDT_RING0_CODE/DATA_SEL with
 constant

MISRA C requires that all unsigned constants should have
the suffix 'U/UL'(e.g. 0xffU), but the assembler may not
accept such C-style constants.

To work this around, HOST_GDT_RING0_CODE_SEL and
HOST_GDT_RING0_DATA_SEL must be explicitly spells
out in assembly with a comment tracking the original
expression from which the magic number is calculated.

V1-->V2:
	Update commit information about HOST_GDT_RING0_CODE_SEL
	and HOST_GDT_RING0_DATA_SEL.
V2-->V3:
	Update comment for HOST_GDT_RING0_CODE_SEL in assembly
	code.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
---
 hypervisor/arch/x86/cpu_primary.S | 9 ++++++---
 hypervisor/arch/x86/idt.S         | 6 ++++--
 hypervisor/arch/x86/trampoline.S  | 7 ++++---
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/hypervisor/arch/x86/cpu_primary.S b/hypervisor/arch/x86/cpu_primary.S
index 76066966e..a4440b4ee 100644
--- a/hypervisor/arch/x86/cpu_primary.S
+++ b/hypervisor/arch/x86/cpu_primary.S
@@ -112,7 +112,8 @@ cpu_primary_start_32:
     lgdt    (%ebx)
 
     /* Perform a long jump based to start executing in 64-bit mode */
-    ljmp    $HOST_GDT_RING0_CODE_SEL, $primary_start_long_mode
+    /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
+    ljmp    $0x0008, $primary_start_long_mode
 
     .code64
     .org 0x200
@@ -150,13 +151,15 @@ primary_start_long_mode:
     rex.w ljmp  *(%rax)
 .data
 jmpbuf: .quad 0
-        .word HOST_GDT_RING0_CODE_SEL
+	/* 0x0008 = HOST_GDT_RING0_CODE_SEL */
+        .word 0x0008
 .text
 after:
     // load all selector registers with appropriate values
     xor     %edx, %edx
     lldt    %dx
-    movl    $HOST_GDT_RING0_DATA_SEL,%eax
+    /* 0x10 = HOST_GDT_RING0_DATA_SEL*/
+    movl    $0x10,%eax
     mov     %eax,%ss  // Was 32bit POC Stack
     mov     %eax,%ds  // Was 32bit POC Data
     mov     %eax,%es  // Was 32bit POC Data
diff --git a/hypervisor/arch/x86/idt.S b/hypervisor/arch/x86/idt.S
index c27540412..0b345413c 100644
--- a/hypervisor/arch/x86/idt.S
+++ b/hypervisor/arch/x86/idt.S
@@ -24,13 +24,15 @@ HOST_IDTR:
  * We'll rearrange and fix up the descriptors at runtime
  */
 .macro interrupt_descriptor entry, dpl=0 ist=0
-	.long	HOST_GDT_RING0_CODE_SEL << 16
+	/* 0x0008 = HOST_GDT_RING0_CODE_SEL */
+	.long	0x0008 << 16
 	.long	0x00008e00 + (dpl << 13) + ist
 	.quad	entry
 .endm
 
 .macro	trap_descriptor entry, dpl=0, ist=0
-	.long	HOST_GDT_RING0_CODE_SEL << 16
+        /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
+	.long	0x0008 << 16
 	.long	0x00008f00 + (dpl <<13) + ist
 	.quad	entry
 .endm
diff --git a/hypervisor/arch/x86/trampoline.S b/hypervisor/arch/x86/trampoline.S
index 73036be89..b8ecf6729 100644
--- a/hypervisor/arch/x86/trampoline.S
+++ b/hypervisor/arch/x86/trampoline.S
@@ -133,14 +133,15 @@ trampoline_fixup_target:
     .global trampoline_start64_fixup
 trampoline_start64_fixup:
     .long   trampoline_start64
-    .word   HOST_GDT_RING0_CODE_SEL
+    /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
+    .word   0x0008
 
     .code64
 trampoline_start64:
 
     /* Set up all other data segment registers */
-
-    movl    $HOST_GDT_RING0_DATA_SEL, %eax
+    /* 0x0010 = HOST_GDT_RING0_DATA_SEL */
+    movl    $0x0010, %eax
     mov     %eax, %ss
     mov     %eax, %ds
     mov     %eax, %es