From 05a4ee807497676dec1967cac2ac232dca04219b Mon Sep 17 00:00:00 2001 From: "Li, Fei1" Date: Wed, 3 Jul 2019 19:54:09 +0800 Subject: [PATCH] hv: cpu: refine secondary cpu start up 1) add a write memory barrier after setting pcpu_sync to one to let this change visible to AP immediately. 2) there's only BSP will set pcpu_sync, so there's no memory order issue between CPUs. Tracked-On: #1842 Signed-off-by: Li, Fei1 Acked-by: Eddie Dong --- hypervisor/arch/x86/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c index fc0cc752a..48eec90b5 100644 --- a/hypervisor/arch/x86/cpu.c +++ b/hypervisor/arch/x86/cpu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -311,7 +310,8 @@ bool start_pcpus(uint64_t mask) uint64_t expected_start_mask = mask; /* secondary cpu start up will wait for pcpu_sync -> 0UL */ - atomic_store64(&pcpu_sync, 1UL); + pcpu_sync = 1UL; + cpu_write_memory_barrier(); i = ffs64(expected_start_mask); while (i != INVALID_BIT_INDEX) { @@ -326,7 +326,7 @@ bool start_pcpus(uint64_t mask) } /* Trigger event to allow secondary CPUs to continue */ - atomic_store64(&pcpu_sync, 0UL); + pcpu_sync = 0UL; return ((pcpu_active_bitmap & mask) == mask); }