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hv: move vmx_rdmsr_pat/vmx_wrmsr_pat from vmcs.c to vmsr.c
This patch moves vmx_rdmsr_pat/vmx_wrmsr_pat from vmcs.c to vmsr.c, so that these two functions would become internal functions inside vmsr.c. This approach improves the modularity. v1 -> v2: * remove 'vmx_rdmsr_pat' * rename 'vmx_wrmsr_pat' with 'write_pat_msr' Tracked-On: #1842 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
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@ -20,46 +20,6 @@
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#include <vmexit.h>
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#include <vmexit.h>
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#include <logmsg.h>
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#include <logmsg.h>
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uint64_t vmx_rdmsr_pat(const struct acrn_vcpu *vcpu)
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{
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/*
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* note: if run_ctx->cr0.CD is set, the actual value in guest's
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* IA32_PAT MSR is PAT_ALL_UC_VALUE, which may be different from
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* the saved value guest_msrs[MSR_IA32_PAT]
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*/
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return vcpu_get_guest_msr(vcpu, MSR_IA32_PAT);
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}
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int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value)
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{
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uint32_t i;
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uint64_t field;
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int32_t ret = 0;
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for (i = 0U; i < 8U; i++) {
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field = (value >> (i * 8U)) & 0xffUL;
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if (pat_mem_type_invalid(field) || ((PAT_FIELD_RSV_BITS & field) != 0UL)) {
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pr_err("invalid guest IA32_PAT: 0x%016llx", value);
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ret = -EINVAL;
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break;
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}
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}
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if (ret == 0) {
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vcpu_set_guest_msr(vcpu, MSR_IA32_PAT, value);
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/*
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* If context->cr0.CD is set, we defer any further requests to write
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* guest's IA32_PAT, until the time when guest's CR0.CD is being cleared
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*/
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if ((vcpu_get_cr0(vcpu) & CR0_CD) == 0UL) {
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, value);
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}
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}
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return ret;
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}
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/* rip, rsp, ia32_efer and rflags are written to VMCS in start_vcpu */
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/* rip, rsp, ia32_efer and rflags are written to VMCS in start_vcpu */
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static void init_guest_vmx(struct acrn_vcpu *vcpu, uint64_t cr0, uint64_t cr3,
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static void init_guest_vmx(struct acrn_vcpu *vcpu, uint64_t cr0, uint64_t cr3,
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uint64_t cr4)
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uint64_t cr4)
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@ -330,6 +330,36 @@ void init_msr_emulation(struct acrn_vcpu *vcpu)
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init_msr_area(vcpu);
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init_msr_area(vcpu);
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}
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}
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static int32_t write_pat_msr(struct acrn_vcpu *vcpu, uint64_t value)
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{
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uint32_t i;
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uint64_t field;
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int32_t ret = 0;
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for (i = 0U; i < 8U; i++) {
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field = (value >> (i * 8U)) & 0xffUL;
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if (pat_mem_type_invalid(field) || ((PAT_FIELD_RSV_BITS & field) != 0UL)) {
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pr_err("invalid guest IA32_PAT: 0x%016llx", value);
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ret = -EINVAL;
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break;
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}
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}
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if (ret == 0) {
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vcpu_set_guest_msr(vcpu, MSR_IA32_PAT, value);
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/*
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* If context->cr0.CD is set, we defer any further requests to write
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* guest's IA32_PAT, until the time when guest's CR0.CD is being cleared
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*/
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if ((vcpu_get_cr0(vcpu) & CR0_CD) == 0UL) {
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, value);
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}
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}
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return ret;
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}
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/**
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/**
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* @pre vcpu != NULL
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* @pre vcpu != NULL
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*/
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*/
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@ -387,7 +417,12 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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}
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}
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case MSR_IA32_PAT:
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case MSR_IA32_PAT:
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{
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{
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v = vmx_rdmsr_pat(vcpu);
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/*
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* note: if run_ctx->cr0.CD is set, the actual value in guest's
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* IA32_PAT MSR is PAT_ALL_UC_VALUE, which may be different from
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* the saved value guest_msrs[MSR_IA32_PAT]
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*/
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v = vcpu_get_guest_msr(vcpu, MSR_IA32_PAT);
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break;
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break;
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}
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}
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case MSR_IA32_APIC_BASE:
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case MSR_IA32_APIC_BASE:
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@ -654,7 +689,7 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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}
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}
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case MSR_IA32_PAT:
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case MSR_IA32_PAT:
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{
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{
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err = vmx_wrmsr_pat(vcpu, v);
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err = write_pat_msr(vcpu, v);
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break;
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break;
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}
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}
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case MSR_IA32_APIC_BASE:
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case MSR_IA32_APIC_BASE:
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@ -55,9 +55,6 @@ static inline uint64_t apic_access_offset(uint64_t qual)
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void init_vmcs(struct acrn_vcpu *vcpu);
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void init_vmcs(struct acrn_vcpu *vcpu);
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uint64_t vmx_rdmsr_pat(const struct acrn_vcpu *vcpu);
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int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value);
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void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
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void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
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static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
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static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
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