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config_tools: generate vDSDT according to allocated resources
This patch generates vDSDT for pre-launched VMs based on the scenario configuration and static allocation results. The vDSDT contains the following objects. * A device object representing the root PCI bus which has the same location and name as the object in physical DSDT. This object contains device identification objects such as _HID, _CID, _BBN and _UID, the _CRS object encoding the bus numbers and PCI hole regions, and the _PRT object encoding the routing from vPCI device pins to virtual interrupt lines. * For each pass-through device assigned to the VM, a device object is created based on the AML template of that device in board XML (if exists). The _ADR object is rewritten with the vBDF.. v1 -> v2: * In order to replace the current static vDSDT, the AML templates in board XMLs now include objects that are referenced by other devices as well. * When TPM is assigned, the corresponding device object in DSDT (if exists) will be copied. * Add the _S5 control method to vDSDT, as is done in the static DSDT sources. * The old vDSDT generation routine and the static DSDT sources it uses are removed. v2 -> v3: * Only follow 'uses', 'is used by' or 'consumes resources by' dependencies. * Organize the device objects in vDSDT according to the scopes they are in. Tracked-On: #6287 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
@@ -1,25 +0,0 @@
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20190703 (64-bit version)
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* Copyright (c) 2000 - 2019 Intel Corporation
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*
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* Original Table Header:
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* Signature "DSDT"
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* Length 0x00000051 (81)
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* Revision 0x03
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* Checksum 0xF0
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* OEM ID "ACRN "
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* OEM Table ID "ACRNDSDT"
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* OEM Revision 0x00000001 (1)
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* Compiler ID "INTL"
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* Compiler Version 0x20190703 (538511107)
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*/
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DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
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{
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Name (_S5, Package ()
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{
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0x05,
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Zero,
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})
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}
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@@ -1,30 +0,0 @@
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20190703 (64-bit version)
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*
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* Original Table Header:
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* Signature "DSDT"
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* Length 0x00000051 (81)
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* Revision 0x03
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* Checksum 0xF0
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* OEM ID "ACRN "
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* OEM Table ID "ACRNDSDT"
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* OEM Revision 0x00000001 (1)
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* Compiler ID "INTL"
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* Compiler Version 0x20190703 (538511107)
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*/
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DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
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{
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Device (TPM)
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{
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Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xFED40000, // Address Base
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0x00005000, // Address Length
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)
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})
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}
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}
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@@ -1,64 +0,0 @@
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20180105 (64-bit version)
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* Copyright (c) 2000 - 2018 Intel Corporation
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*
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* Original Table Header:
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* Signature "DSDT"
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* Length 0x00000102 (258)
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* Revision 0x03
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* Checksum 0x08
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* OEM ID "ACRN "
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* OEM Table ID "ACRNDSDT"
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* OEM Revision 0x00000001 (1)
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* Compiler ID "INTL"
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* Compiler Version 0x20180105 (538444037)
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*/
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DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
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{
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Scope (_SB)
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{
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Device (OTN1)
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{
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Name (_ADR, 0x00020000) // _ADR: Address
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OperationRegion (TSRT, PCI_Config, Zero, 0x0100)
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Field (TSRT, AnyAcc, NoLock, Preserve)
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{
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DVID, 16,
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Offset (0x10),
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TADL, 32,
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TADH, 32
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}
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}
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Device (PCS2)
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{
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Name (_HID, "INTC1033") // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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Return (0x0F)
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}
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Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
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{
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Name (PCSR, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite,
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0x00000000, // Address Base
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0x00000004, // Address Length
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_Y00)
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Memory32Fixed (ReadWrite,
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0x00000000, // Address Base
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0x00000004, // Address Length
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_Y01)
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})
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CreateDWordField (PCSR, \_SB.PCS2._CRS._Y00._BAS, MAL0) // _BAS: Base Address
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MAL0 = ((^^OTN1.TADL & 0xFFFFF000) + 0x0200)
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CreateDWordField (PCSR, \_SB.PCS2._CRS._Y01._BAS, MDL0) // _BAS: Base Address
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MDL0 = ((^^OTN1.TADL & 0xFFFFF000) + 0x0204)
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Return (PCSR) /* \_SB_.PCS2._CRS.PCSR */
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}
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}
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}
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}
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