github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-09-03 09:55:01 +00:00
Code Issues Projects Releases Wiki Activity

dm:Remove deprecated terms

Browse Source 
- remove usages of maste/slave:

Tracked-On: #5249
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
2020-08-28 14:51:24 +08:00
committed by wenlingz
parent c03623f3fb
commit 07ed6841f5
10 changed files with 64 additions and 1786 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
devicemodel/include/pcireg.h
View File

@@ -87,7 +87,7 @@
#define PCIR_COMMAND 0x04
#define PCIM_CMD_PORTEN 0x0001
#define PCIM_CMD_MEMEN 0x0002
#define PCIM_CMD_BUSMASTEREN 0x0004
#define PCIM_CMD_BUSHOSTEN 0x0004
#define PCIM_CMD_SPECIALEN 0x0008
#define PCIM_CMD_MWRICEN 0x0010
#define PCIM_CMD_PERRESPEN 0x0040
@@ -322,7 +322,7 @@
#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
#define PCIP_STORAGE_IDE_MODESEC 0x04
#define PCIP_STORAGE_IDE_PROGINDSEC 0x08
#define PCIP_STORAGE_IDE_MASTERDEV 0x80
#define PCIP_STORAGE_IDE_HOSTDEV 0x80
#define PCIS_STORAGE_FLOPPY 0x02
#define PCIS_STORAGE_IPI 0x03
#define PCIS_STORAGE_RAID 0x04
@@ -493,7 +493,7 @@
#define PCIB_BCR_SERR_ENABLE 0x0002
#define PCIB_BCR_ISA_ENABLE 0x0004
#define PCIB_BCR_VGA_ENABLE 0x0008
#define PCIB_BCR_MASTER_ABORT_MODE 0x0020
#define PCIB_BCR_HOST_ABORT_MODE 0x0020
#define PCIB_BCR_SECBUS_RESET 0x0040
#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
@@ -505,7 +505,7 @@
#define CBB_BCR_SERR_ENABLE 0x0002
#define CBB_BCR_ISA_ENABLE 0x0004
#define CBB_BCR_VGA_ENABLE 0x0008
#define CBB_BCR_MASTER_ABORT_MODE 0x0020
#define CBB_BCR_HOST_ABORT_MODE 0x0020
#define CBB_BCR_CARDBUS_RESET 0x0040
#define CBB_BCR_IREQ_INT_ENABLE 0x0080
#define CBB_BCR_PREFETCH_0_ENABLE 0x0100
@@ -717,7 +717,7 @@
/* HT (HyperTransport) Capability definitions */
#define PCIR_HT_COMMAND 0x2
#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
#define PCIM_HTCAP_CLIENT 0x0000 /* 000xx */
#define PCIM_HTCAP_HOST 0x2000 /* 001xx */
#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */