diff --git a/hypervisor/arch/riscv/Makefile b/hypervisor/arch/riscv/Makefile
index 1c49b8986..1c3f122da 100644
--- a/hypervisor/arch/riscv/Makefile
+++ b/hypervisor/arch/riscv/Makefile
@@ -61,6 +61,7 @@ HOST_C_SRCS += arch/riscv/mmu.c
 HOST_C_SRCS += arch/riscv/irq.c
 HOST_C_SRCS += arch/riscv/pgtable.c
 HOST_C_SRCS += arch/riscv/security.c
+HOST_C_SRCS += arch/riscv/pm.c
 
 # Virtual platform assembly sources
 VP_S_SRCS +=
diff --git a/hypervisor/arch/riscv/pm.c b/hypervisor/arch/riscv/pm.c
new file mode 100644
index 000000000..61389b101
--- /dev/null
+++ b/hypervisor/arch/riscv/pm.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <types.h>
+#include <host_pm.h>
+#include <asm/sbi.h>
+
+static const char *reset_mode_str[] = {
+	"shutdown",
+	"cold reboot",
+	"warm reboot",
+};
+
+static void sbi_system_reset(uint32_t rst_type, uint32_t rst_reason)
+{
+	sbiret ret;
+
+	ret = sbi_ecall(rst_type, rst_reason, 0, 0, 0, 0, SBI_EXT_SRST_RESET, SBI_EID_SRST);
+
+	/* above sbi call will not return if succeeded */
+	panic("Failed to %s system, ret 0x%x", reset_mode_str[rst_type], ret.error);
+}
+
+void arch_shutdown_host()
+{
+	sbi_system_reset(SBI_SRST_RESET_TYPE_SHUTDOWN, 0U);
+}
+
+void arch_reset_host(bool warm)
+{
+	sbi_system_reset(warm ? SBI_SRST_RESET_TYPE_WARM_REBOOT \
+			: SBI_SRST_RESET_TYPE_COLD_REBOOT, 0U);
+}
diff --git a/hypervisor/include/arch/riscv/asm/host_pm.h b/hypervisor/include/arch/riscv/asm/host_pm.h
index a9b2f654b..c11775fc4 100644
--- a/hypervisor/include/arch/riscv/asm/host_pm.h
+++ b/hypervisor/include/arch/riscv/asm/host_pm.h
@@ -6,9 +6,4 @@
 #ifndef	RISCV_HOST_PM_H
 #define	RISCV_HOST_PM_H
 
-/* FIXME: To be implemented */
-static inline void arch_shutdown_host(void) { }
-/* FIXME: To be implemented */
-static inline void arch_reset_host(bool warm) { (void)warm; }
-
 #endif	/* RISCV_HOST_PM_H */