From 090aaf4c34ba98b4f517a6353113e5d7cc73f55c Mon Sep 17 00:00:00 2001
From: Haicheng Li <haicheng.li@intel.com>
Date: Sun, 7 Sep 2025 11:27:56 +0800
Subject: [PATCH] hv: multi-arch add RISC-V barrier library implementation

Follow multi-arch design, implement the mandatory arch barrier
functions declared in common barrier.h for risc-v support.

Tracked-On: #8803
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Co-developed-by: Haoyu Tang <haoyu.tang@intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
---
 hypervisor/include/arch/riscv/asm/cpu.h       |  4 +--
 .../include/arch/riscv/asm/lib/barrier.h      | 28 +++++++++++++++++++
 2 files changed, 30 insertions(+), 2 deletions(-)
 create mode 100644 hypervisor/include/arch/riscv/asm/lib/barrier.h

diff --git a/hypervisor/include/arch/riscv/asm/cpu.h b/hypervisor/include/arch/riscv/asm/cpu.h
index 07c628bf6..5f8c5f662 100644
--- a/hypervisor/include/arch/riscv/asm/cpu.h
+++ b/hypervisor/include/arch/riscv/asm/cpu.h
@@ -12,9 +12,9 @@
 #include <lib/util.h>
 #include <debug/logmsg.h>
 #include <board_info.h>
+#include <barrier.h>
 
-#define barrier()	__asm__ __volatile__("fence": : :"memory")
-#define cpu_relax()	barrier() /* TODO: replace with yield instruction */
+#define cpu_relax()	cpu_memory_barrier() /* TODO: replace with yield instruction */
 #define NR_CPUS		MAX_PCPU_NUM
 
 #define LONG_BYTEORDER 3
diff --git a/hypervisor/include/arch/riscv/asm/lib/barrier.h b/hypervisor/include/arch/riscv/asm/lib/barrier.h
new file mode 100644
index 000000000..3bb5e8321
--- /dev/null
+++ b/hypervisor/include/arch/riscv/asm/lib/barrier.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Authors:
+ *   Haicheng Li <haicheng.li@intel.com>
+ */
+
+#ifndef RISCV_LIB_BARRIER_H
+#define RISCV_LIB_BARRIER_H
+/* Synchronizes all read accesses to/from memory */
+static inline void arch_cpu_read_memory_barrier(void)
+{
+	asm volatile ("fence r,r" : : : "memory");
+}
+
+static inline void arch_cpu_write_memory_barrier(void)
+{
+	asm volatile ("fence w,w" : : : "memory");
+}
+
+/* Synchronizes all read and write accesses to/from memory */
+static inline void arch_cpu_memory_barrier(void)
+{
+	asm volatile ("fence rw,rw" : : : "memory");
+}
+#endif /* RISCV_LIB_BARRIER_H */