hv:Change structure boot_cpu_data to static

-- Change boot_cpu_data to static, only used in cpu_caps.c,
-- Add get_cpu_info() api, it will call this api instead of
   boot_cpu_data except cpu_caps.c

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>

hypervisor/arch/x86/cpu.c

@@ -163,7 +163,7 @@ void init_cpu_post(uint16_t pcpu_id)
 		pr_acrnlog("API version %u.%u",
 				HV_API_MAJOR_VERSION, HV_API_MINOR_VERSION);
 
-		pr_acrnlog("Detect processor: %s", boot_cpu_data.model_name);
+		pr_acrnlog("Detect processor: %s", (get_cpu_info())->model_name);
 
 		pr_dbg("Core %hu is up", BOOT_CPU_ID);
 
@@ -393,6 +393,7 @@ void wait_sync_change(uint64_t *sync, uint64_t wake_sync)
 static void cpu_xsave_init(void)
 {
 	uint64_t val64;
+	struct cpuinfo_x86 *cpu_info;
 
 	if (cpu_has_cap(X86_FEATURE_XSAVE)) {
 		CPU_CR_READ(cr4, &val64);
@@ -405,8 +406,8 @@ static void cpu_xsave_init(void)
 
 			/* if set, update it */
 			if ((ecx & CPUID_ECX_OSXSAVE) != 0U) {
-				boot_cpu_data.cpuid_leaves[FEAT_1_ECX] |=
+				cpu_info = get_cpu_info();
-						CPUID_ECX_OSXSAVE;
+				cpu_info->cpuid_leaves[FEAT_1_ECX] |= CPUID_ECX_OSXSAVE;
 			}
 		}
 	}

hypervisor/arch/x86/cpu_caps.c

@@ -34,7 +34,7 @@ static struct cpu_capability {
 	uint32_t vmx_vpid;
 } cpu_caps;
 
-struct cpuinfo_x86 boot_cpu_data;
+static struct cpuinfo_x86 boot_cpu_data;
 
 bool cpu_has_cap(uint32_t bit)
 {
@@ -417,3 +417,8 @@ int32_t detect_hardware_support(void)
 
 	return ret;
 }
+
+struct cpuinfo_x86 *get_cpu_info(void)
+{
+	return &boot_cpu_data;
+}

hypervisor/arch/x86/cpu_state_tbl.c

@@ -131,10 +131,11 @@ void load_cpu_state_data(void)
 {
 	int32_t tbl_idx;
 	const struct cpu_state_info *state_info;
+	struct cpuinfo_x86 *cpu_info = get_cpu_info();
 
 	(void)memset(&cpu_pm_state_info, 0U, sizeof(struct cpu_state_info));
 
-	tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name);
+	tbl_idx = get_state_tbl_idx(cpu_info->model_name);
 
 	if (tbl_idx >= 0) {
 		/* The state table is found. */

hypervisor/arch/x86/guest/vcpuid.c

@@ -97,6 +97,8 @@ static inline int32_t set_vcpuid_entry(struct acrn_vm *vm,
 static void init_vcpuid_entry(uint32_t leaf, uint32_t subleaf,
 			uint32_t flags, struct vcpuid_entry *entry)
 {
+	struct cpuinfo_x86 *cpu_info;
+
 	entry->leaf = leaf;
 	entry->subleaf = subleaf;
 	entry->flags = flags;
@@ -123,7 +125,8 @@ static void init_vcpuid_entry(uint32_t leaf, uint32_t subleaf,
 		break;
 
 	case 0x16U:
-		if (boot_cpu_data.cpuid_level >= 0x16U) {
+		cpu_info = get_cpu_info();
+		if (cpu_info->cpuid_level >= 0x16U) {
 			/* call the cpuid when 0x16 is supported */
 			cpuid_subleaf(leaf, subleaf, &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
 		} else {
@@ -185,9 +188,10 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
 	struct vcpuid_entry entry;
 	uint32_t limit;
 	uint32_t i, j;
+	struct cpuinfo_x86 *cpu_info = get_cpu_info();
 
 	init_vcpuid_entry(0U, 0U, 0U, &entry);
-	if (boot_cpu_data.cpuid_level < 0x16U) {
+	if (cpu_info->cpuid_level < 0x16U) {
 		/* The cpuid with zero leaf returns the max level. Emulate that the 0x16U is supported */
 		entry.eax = 0x16U;
 	}

hypervisor/arch/x86/lapic.c

@@ -196,6 +196,7 @@ send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
 {
 	union apic_icr icr;
 	uint8_t shorthand;
+	struct cpuinfo_x86 *cpu_info = get_cpu_info();
 
 	icr.value = 0U;
 	icr.bits.destination_mode = INTR_LAPIC_ICR_PHYSICAL;
@@ -218,7 +219,7 @@ send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
 	/* Give 10ms for INIT sequence to complete for old processors.
 	 * Modern processors (family == 6) don't need to wait here.
 	 */
-	if (boot_cpu_data.family != 6U) {
+	if (cpu_info->family != 6U) {
 		/* delay 10ms */
 		udelay(10000U);
 	}
@@ -234,7 +235,7 @@ send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
 	icr.bits.vector = (uint8_t)(cpu_startup_start_address >> 12U);
 	msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
 
-	if (boot_cpu_data.family == 6U) {
+	if (cpu_info->family == 6U) {
 		udelay(10U); /* 10us is enough for Modern processors */
 	} else {
 		udelay(200U); /* 200us for old processors */

hypervisor/arch/x86/timer.c

@@ -245,8 +245,9 @@ static uint64_t pit_calibrate_tsc(uint32_t cal_ms_arg)
 static uint64_t native_calibrate_tsc(void)
 {
 	uint64_t tsc_hz = 0UL;
+	struct cpuinfo_x86 *cpu_info = get_cpu_info();
 
-	if (boot_cpu_data.cpuid_level >= 0x15U) {
+	if (cpu_info->cpuid_level >= 0x15U) {
 		uint32_t eax_denominator, ebx_numerator, ecx_hz, reserved;
 
 		cpuid(0x15U, &eax_denominator, &ebx_numerator,
@@ -258,7 +259,7 @@ static uint64_t native_calibrate_tsc(void)
 		}
 	}
 
-	if ((tsc_hz == 0UL) && (boot_cpu_data.cpuid_level >= 0x16U)) {
+	if ((tsc_hz == 0UL) && (cpu_info->cpuid_level >= 0x16U)) {
 		uint32_t eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
 		cpuid(0x16U, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
 		tsc_hz = (uint64_t) eax_base_mhz * 1000000U;

hypervisor/include/arch/x86/cpu_caps.h

@@ -36,8 +36,6 @@ struct cpuinfo_x86 {
 	char model_name[64];
 };
 
-extern struct cpuinfo_x86 boot_cpu_data;
-
 bool has_monitor_cap(void);
 bool is_apicv_reg_virtualization_supported(void);
 bool is_apicv_intr_delivery_supported(void);
@@ -50,5 +48,6 @@ void init_cpu_model_name(void);
 bool check_cpu_security_cap(void);
 void cpu_l1d_flush(void);
 int detect_hardware_support(void);
+struct cpuinfo_x86 *get_cpu_info(void);
 
 #endif /* CPUINFO_H */

hypervisor/include/arch/x86/mmu.h

@@ -51,8 +51,7 @@
 #define CACHE_LINE_SIZE		64U
 
 /* IA32E Paging constants */
-#define IA32E_REF_MASK		\
+#define IA32E_REF_MASK	((get_cpu_info())->physical_address_mask)
-		(boot_cpu_data.physical_address_mask)
 
 extern uint8_t ld_text_end;