mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-01 03:45:29 +00:00
hv: instr_emul: clean up mmio_read/mmio_write
clean up mmio_read/mmio_write in instr_emul.c - make these two functions inline - discard the return value and add the pre condition - rename these two functions to vie_mmio_read/vie_mmio_write Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao
lijinxia
parent
2c7c909e38
commit
0a9d6841f7
@ -492,24 +492,20 @@ static int vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum cpu_reg_name seg,
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return 0;
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}
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static int mmio_read(const struct acrn_vcpu *vcpu, uint64_t *rval)
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/*
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* @pre vcpu != NULL
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*/
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static inline void vie_mmio_read(const struct acrn_vcpu *vcpu, uint64_t *rval)
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{
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if (vcpu == NULL) {
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return -EINVAL;
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}
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*rval = vcpu->req.reqs.mmio.value;
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return 0;
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}
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static int mmio_write(struct acrn_vcpu *vcpu, uint64_t wval)
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/*
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* @pre vcpu != NULL
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*/
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static inline void vie_mmio_write(struct acrn_vcpu *vcpu, uint64_t wval)
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{
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if (vcpu == NULL) {
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return -EINVAL;
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}
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vcpu->req.reqs.mmio.value = wval;
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return 0;
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}
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static void vie_calc_bytereg(const struct instr_emul_vie *vie,
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@ -673,7 +669,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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uint64_t val;
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size = vie->opsize;
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error = -EINVAL;
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error = 0;
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switch (vie->opcode) {
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case 0x88U:
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/*
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@ -683,7 +679,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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*/
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size = 1U; /* override for byte operation */
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byte = vie_read_bytereg(vcpu, vie);
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error = mmio_write(vcpu, byte);
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vie_mmio_write(vcpu, byte);
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break;
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case 0x89U:
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/*
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@ -696,7 +692,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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reg = vie->reg;
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val = vm_get_register(vcpu, reg);
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val &= size2mask[size];
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error = mmio_write(vcpu, val);
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vie_mmio_write(vcpu, val);
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break;
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case 0x8AU:
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/*
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@ -705,10 +701,8 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* REX + 8A/r: mov r8, r/m8
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*/
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size = 1U; /* override for byte operation */
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error = mmio_read(vcpu, &val);
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if (error == 0) {
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vie_write_bytereg(vcpu, vie, (uint8_t)val);
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}
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vie_mmio_read(vcpu, &val);
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vie_write_bytereg(vcpu, vie, (uint8_t)val);
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break;
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case 0x8BU:
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/*
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@ -717,11 +711,9 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* 8B/r: mov r32, r/m32
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* REX.W 8B/r: mov r64, r/m64
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*/
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error = mmio_read(vcpu, &val);
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if (error == 0) {
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reg = vie->reg;
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vie_update_register(vcpu, reg, val, size);
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}
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vie_mmio_read(vcpu, &val);
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reg = vie->reg;
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vie_update_register(vcpu, reg, val, size);
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break;
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case 0xA1U:
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/*
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@ -730,11 +722,9 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* A1: mov EAX, moffs32
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* REX.W + A1: mov RAX, moffs64
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*/
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error = mmio_read(vcpu, &val);
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if (error == 0) {
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reg = CPU_REG_RAX;
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vie_update_register(vcpu, reg, val, size);
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}
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vie_mmio_read(vcpu, &val);
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reg = CPU_REG_RAX;
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vie_update_register(vcpu, reg, val, size);
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break;
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case 0xA3U:
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/*
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@ -745,7 +735,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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*/
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val = vm_get_register(vcpu, CPU_REG_RAX);
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val &= size2mask[size];
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error = mmio_write(vcpu, val);
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vie_mmio_write(vcpu, val);
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break;
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case 0xC6U:
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/*
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@ -754,7 +744,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* REX + C6/0 mov r/m8, imm8
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*/
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size = 1U; /* override for byte operation */
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error = mmio_write(vcpu, (uint64_t)vie->immediate);
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vie_mmio_write(vcpu, (uint64_t)vie->immediate);
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break;
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case 0xC7U:
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/*
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@ -765,7 +755,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* (sign-extended to 64-bits)
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*/
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val = (uint64_t)vie->immediate & size2mask[size];
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error = mmio_write(vcpu, val);
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vie_mmio_write(vcpu, val);
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break;
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default:
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/*
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@ -774,6 +764,7 @@ static int emulate_mov(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* Gracefully return this error code if prior case clauses have
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* not been met.
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*/
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error = -EINVAL;
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break;
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}
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@ -788,7 +779,7 @@ static int emulate_movx(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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uint64_t val;
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size = vie->opsize;
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error = -EINVAL;
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error = 0;
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switch (vie->opcode) {
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case 0xB6U:
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@ -802,10 +793,7 @@ static int emulate_movx(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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*/
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/* get the first operand */
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error = mmio_read(vcpu, &val);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val);
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/* get the second operand */
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reg = vie->reg;
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@ -824,10 +812,7 @@ static int emulate_movx(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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* 0F B7/r movzx r32, r/m16
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* REX.W + 0F B7/r movzx r64, r/m16
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*/
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error = mmio_read(vcpu, &val);
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if (error != 0) {
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return error;
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}
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vie_mmio_read(vcpu, &val);
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reg = vie->reg;
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@ -847,10 +832,7 @@ static int emulate_movx(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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*/
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/* get the first operand */
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error = mmio_read(vcpu, &val);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val);
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/* get the second operand */
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reg = vie->reg;
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@ -868,6 +850,7 @@ static int emulate_movx(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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* Gracefully return this error code if prior case clauses have
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* not been met.
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*/
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error = -EINVAL;
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break;
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}
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return error;
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@ -1026,9 +1009,9 @@ static int emulate_movs(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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src_hva = gpa2hva(vcpu->vm, gpa);
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(void)memcpy_s(&val, opsize, src_hva, opsize);
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mmio_write(vcpu, val);
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vie_mmio_write(vcpu, val);
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} else {
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mmio_read(vcpu, &val);
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vie_mmio_read(vcpu, &val);
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/* The dest gpa is saved during dst check instruction
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* decoding.
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@ -1069,7 +1052,7 @@ done:
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static int emulate_stos(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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{
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int error, repeat;
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int repeat;
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uint8_t opsize = vie->opsize;
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uint64_t val;
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uint64_t rcx, rdi, rflags;
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@ -1090,10 +1073,7 @@ static int emulate_stos(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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val = vm_get_register(vcpu, CPU_REG_RAX);
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error = mmio_write(vcpu, val);
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if (error != 0) {
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return error;
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}
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vie_mmio_write(vcpu, val);
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rdi = vm_get_register(vcpu, CPU_REG_RDI);
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rflags = vm_get_register(vcpu, CPU_REG_RFLAGS);
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@ -1129,7 +1109,7 @@ static int emulate_test(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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uint64_t result, rflags2, val1, val2;
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size = vie->opsize;
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error = -EINVAL;
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error = 0;
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switch (vie->opcode) {
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case 0x84U:
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@ -1154,10 +1134,7 @@ static int emulate_test(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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val1 = vm_get_register(vcpu, reg);
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/* get the second operand */
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error = mmio_read(vcpu, &val2);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val2);
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/* perform the operation and write the result */
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result = val1 & val2;
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@ -1169,6 +1146,7 @@ static int emulate_test(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie
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* Gracefully return this error code if prior case clauses have
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* not been met.
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*/
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error = -EINVAL;
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break;
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}
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@ -1195,7 +1173,7 @@ static int emulate_and(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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uint64_t result, rflags2, val1, val2;
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size = vie->opsize;
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error = -EINVAL;
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error = 0;
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switch (vie->opcode) {
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case 0x23U:
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@ -1213,10 +1191,7 @@ static int emulate_and(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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val1 = vm_get_register(vcpu, reg);
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/* get the second operand */
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error = mmio_read(vcpu, &val2);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val2);
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/* perform the operation and write the result */
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result = val1 & val2;
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@ -1238,17 +1213,14 @@ static int emulate_and(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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*/
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/* get the first operand */
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error = mmio_read(vcpu, &val1);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val1);
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/*
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* perform the operation with the pre-fetched immediate
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* operand and write the result
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*/
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result = val1 & vie->immediate;
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error = mmio_write(vcpu, result);
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vie_mmio_write(vcpu, result);
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break;
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default:
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/*
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@ -1257,6 +1229,7 @@ static int emulate_and(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* Gracefully return this error code if prior case clauses have
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* not been met.
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*/
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error = -EINVAL;
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break;
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}
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@ -1283,7 +1256,7 @@ static int emulate_or(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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uint64_t val1, val2, result, rflags2;
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size = vie->opsize;
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error = -EINVAL;
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error = 0;
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switch (vie->opcode) {
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case 0x81U:
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@ -1306,17 +1279,14 @@ static int emulate_or(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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*/
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/* get the first operand */
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error = mmio_read(vcpu, &val1);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val1);
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/*
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* perform the operation with the pre-fetched immediate
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* operand and write the result
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*/
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result = val1 | (uint64_t)vie->immediate;
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error = mmio_write(vcpu, result);
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vie_mmio_write(vcpu, result);
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break;
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case 0x09U:
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/*
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@ -1327,10 +1297,7 @@ static int emulate_or(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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*/
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/* get the first operand */
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error = mmio_read(vcpu, &val1);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val1);
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/* get the second operand */
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reg = vie->reg;
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@ -1340,7 +1307,7 @@ static int emulate_or(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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result = val1 | val2;
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result &= size2mask[size];
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error = mmio_write(vcpu, result);
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vie_mmio_write(vcpu, result);
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break;
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default:
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/*
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@ -1349,6 +1316,7 @@ static int emulate_or(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* Gracefully return this error code if prior case clauses have
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* not been met.
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*/
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error = -EINVAL;
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break;
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}
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if (error == 0) {
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@ -1397,10 +1365,7 @@ static int emulate_cmp(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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regop = vm_get_register(vcpu, reg);
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/* Get the memory operand */
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error = mmio_read(vcpu, &memop);
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if (error != 0) {
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return error;
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}
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vie_mmio_read(vcpu, &memop);
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if (vie->opcode == 0x3BU) {
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op1 = regop;
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@ -1442,10 +1407,7 @@ static int emulate_cmp(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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}
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/* get the first operand */
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error = mmio_read(vcpu, &op1);
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if (error != 0) {
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return error;
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}
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vie_mmio_read(vcpu, &op1);
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rflags2 = getcc(size, op1, (uint64_t)vie->immediate);
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break;
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@ -1466,7 +1428,7 @@ static int emulate_sub(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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enum cpu_reg_name reg;
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size = vie->opsize;
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error = -EINVAL;
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error = 0;
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switch (vie->opcode) {
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case 0x2BU:
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@ -1483,10 +1445,7 @@ static int emulate_sub(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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val1 = vm_get_register(vcpu, reg);
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/* get the second operand */
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error = mmio_read(vcpu, &val2);
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if (error != 0) {
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break;
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}
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vie_mmio_read(vcpu, &val2);
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/* perform the operation and write the result */
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nval = val1 - val2;
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@ -1499,6 +1458,7 @@ static int emulate_sub(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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* Gracefully return this error code if prior case clauses have
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* not been met.
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*/
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error = -EINVAL;
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break;
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}
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@ -1537,7 +1497,6 @@ static int emulate_group1(struct acrn_vcpu *vcpu, const struct instr_emul_vie *v
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static int emulate_bittest(struct acrn_vcpu *vcpu, const struct instr_emul_vie *vie)
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{
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uint64_t val, rflags, bitmask;
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int error;
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uint64_t bitoff;
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uint8_t size;
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@ -1553,10 +1512,7 @@ static int emulate_bittest(struct acrn_vcpu *vcpu, const struct instr_emul_vie *
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rflags = vm_get_register(vcpu, CPU_REG_RFLAGS);
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error = mmio_read(vcpu, &val);
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if (error != 0) {
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return error;
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}
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vie_mmio_read(vcpu, &val);
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/*
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* Intel SDM, Vol 2, Table 3-2:
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