diff --git a/hypervisor/Makefile b/hypervisor/Makefile index e18495c51..85667896c 100644 --- a/hypervisor/Makefile +++ b/hypervisor/Makefile @@ -45,9 +45,9 @@ default: all include scripts/makefile/config.mk -BOARD_INFO_DIR := $(HV_CONFIG_DIR)/boards/$(BOARD) +BOARD_INFO_DIR := $(HV_CONFIG_DIR)/boards SCENARIO_CFG_DIR := $(HV_CONFIG_DIR)/scenarios/$(SCENARIO) -BOARD_CFG_DIR := $(SCENARIO_CFG_DIR)/$(BOARD) +BOARD_CFG_DIR := $(SCENARIO_CFG_DIR) include ../paths.make diff --git a/misc/config_tools/acpi_gen/asl_gen.py b/misc/config_tools/acpi_gen/asl_gen.py index 3a1b89527..b9a7e7270 100644 --- a/misc/config_tools/acpi_gen/asl_gen.py +++ b/misc/config_tools/acpi_gen/asl_gen.py @@ -402,9 +402,9 @@ def main(args): if isinstance(pcpu_list, list): pcpu_list = [x.strip() for x in pcpu_list] if out is None or out == '': - DEST_ACPI_PATH = os.path.join(VM_CONFIGS_PATH, 'scenarios', scenario_name, board_type) + DEST_ACPI_PATH = os.path.join(VM_CONFIGS_PATH, 'scenarios', scenario_name) else: - DEST_ACPI_PATH = os.path.join(common.SOURCE_ROOT_DIR, out, 'scenarios', scenario_name, board_type) + DEST_ACPI_PATH = os.path.join(common.SOURCE_ROOT_DIR, out, 'scenarios', scenario_name) if os.path.isdir(DEST_ACPI_PATH): for config in os.listdir(DEST_ACPI_PATH): diff --git a/misc/config_tools/acpi_gen/bin_gen.py b/misc/config_tools/acpi_gen/bin_gen.py index 3c6416a63..dc2776be0 100644 --- a/misc/config_tools/acpi_gen/bin_gen.py +++ b/misc/config_tools/acpi_gen/bin_gen.py @@ -169,9 +169,9 @@ def main(args): board_type = args.board scenario_name = args.scenario if args.asl is None: - DEST_ACPI_PATH = os.path.join(VM_CONFIGS_PATH, 'scenarios', scenario_name, board_type) + DEST_ACPI_PATH = os.path.join(VM_CONFIGS_PATH, 'scenarios', scenario_name) else: - DEST_ACPI_PATH = os.path.join(common.SOURCE_ROOT_DIR, args.asl, 'scenarios', scenario_name, board_type) + DEST_ACPI_PATH = os.path.join(common.SOURCE_ROOT_DIR, args.asl, 'scenarios', scenario_name) if args.out is None: DEST_ACPI_BIN_PATH = os.path.join(common.SOURCE_ROOT_DIR, 'build', 'hypervisor', 'acpi') else: diff --git a/misc/config_tools/board_config/board_cfg_gen.py b/misc/config_tools/board_config/board_cfg_gen.py index 1f1ad0d9a..17c8f281f 100755 --- a/misc/config_tools/board_config/board_cfg_gen.py +++ b/misc/config_tools/board_config/board_cfg_gen.py @@ -75,8 +75,8 @@ def main(args): else: output = ACRN_CONFIG_DEF - board_fix_dir = os.path.join(output, "boards/" + board + '/') - scen_board_dir = os.path.join(output, "scenarios/" + scenario + "/" + board + '/') + board_fix_dir = os.path.join(output, "boards/") + scen_board_dir = os.path.join(output, "scenarios/" + scenario + "/") common.mkdir(board_fix_dir) common.mkdir(scen_board_dir) diff --git a/misc/config_tools/data/generic/generic.xml b/misc/config_tools/data/generic_board/generic_board.xml similarity index 99% rename from misc/config_tools/data/generic/generic.xml rename to misc/config_tools/data/generic_board/generic_board.xml index 09ffe4775..22f7777f0 100644 --- a/misc/config_tools/data/generic/generic.xml +++ b/misc/config_tools/data/generic_board/generic_board.xml @@ -1,4 +1,4 @@ - + BIOS Information Vendor: Intel Corporation diff --git a/misc/config_tools/data/generic_board/generic_code/boards/board.c b/misc/config_tools/data/generic_board/generic_code/boards/board.c new file mode 100644 index 000000000..37a4cb19e --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/boards/board.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: Intel Corporation + * Version: EHLSFWI1.R00.2224.A00.2005281500 + * Release Date: 05/28/2020 + * + * Base Board Information + * Manufacturer: Intel Corporation + * Product Name: ElkhartLake LPDDR4x T3 CRB + * Version: 2 + */ + +#include +#include +#include +#include +#include + +static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = { + { + .type = DRHD0_DEVSCOPE0_TYPE, + .id = DRHD0_DEVSCOPE0_ID, + .bus = DRHD0_DEVSCOPE0_BUS, + .devfun = DRHD0_DEVSCOPE0_PATH, + }, +}; + +static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = { + { + .type = DRHD1_DEVSCOPE0_TYPE, + .id = DRHD1_DEVSCOPE0_ID, + .bus = DRHD1_DEVSCOPE0_BUS, + .devfun = DRHD1_DEVSCOPE0_PATH, + }, + { + .type = DRHD1_DEVSCOPE1_TYPE, + .id = DRHD1_DEVSCOPE1_ID, + .bus = DRHD1_DEVSCOPE1_BUS, + .devfun = DRHD1_DEVSCOPE1_PATH, + }, +}; + +static struct dmar_dev_scope drhd2_dev_scope[DRHD2_DEV_CNT] = { + { + .type = DRHD2_DEVSCOPE0_TYPE, + .id = DRHD2_DEVSCOPE0_ID, + .bus = DRHD2_DEVSCOPE0_BUS, + .devfun = DRHD2_DEVSCOPE0_PATH, + }, + { + .type = DRHD2_DEVSCOPE1_TYPE, + .id = DRHD2_DEVSCOPE1_ID, + .bus = DRHD2_DEVSCOPE1_BUS, + .devfun = DRHD2_DEVSCOPE1_PATH, + }, + { + .type = DRHD2_DEVSCOPE2_TYPE, + .id = DRHD2_DEVSCOPE2_ID, + .bus = DRHD2_DEVSCOPE2_BUS, + .devfun = DRHD2_DEVSCOPE2_PATH, + }, +}; + +static struct dmar_drhd drhd_info_array[DRHD_COUNT] = { + { + .dev_cnt = DRHD0_DEV_CNT, + .segment = DRHD0_SEGMENT, + .flags = DRHD0_FLAGS, + .reg_base_addr = DRHD0_REG_BASE, + .ignore = DRHD0_IGNORE, + .devices = drhd0_dev_scope + }, + { + .dev_cnt = DRHD1_DEV_CNT, + .segment = DRHD1_SEGMENT, + .flags = DRHD1_FLAGS, + .reg_base_addr = DRHD1_REG_BASE, + .ignore = DRHD1_IGNORE, + .devices = drhd1_dev_scope + }, + { + .dev_cnt = DRHD2_DEV_CNT, + .segment = DRHD2_SEGMENT, + .flags = DRHD2_FLAGS, + .reg_base_addr = DRHD2_REG_BASE, + .ignore = DRHD2_IGNORE, + .devices = drhd2_dev_scope + }, +}; + +struct dmar_info plat_dmar_info = { + .drhd_count = DRHD_COUNT, + .drhd_units = drhd_info_array, +}; + +#ifdef CONFIG_RDT_ENABLED +struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES]; +struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES]; +struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES]; +#endif + +static const struct cpu_cx_data board_cpu_cx[3] = { + {{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */ + {{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0xFDU, 0x00U}, /* C2 */ + {{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x418U, 0x00U}, /* C3 */ +}; + +static const struct cpu_px_data board_cpu_px[2] = { + {0x5DDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P0 */ + {0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P1 */ +}; + +const struct cpu_state_table board_cpu_state_tbl = { + "Genuine Intel(R) CPU 0000 @ 1.50GHz", + {(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px, + (uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx} +}; +const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; + +#define VMSIX_ON_MSI_DEV0 .bdf.bits = {.b = 0x00U, .d = 0x1eU, .f =0x4U}, +#define VMSIX_ON_MSI_DEV1 .bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x1U}, +#define VMSIX_ON_MSI_DEV2 .bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x2U}, +#define VMSIX_ON_MSI_DEV3 .bdf.bits = {.b = 0x00U, .d = 0x13U, .f =0x4U}, +#define VMSIX_ON_MSI_DEV4 .bdf.bits = {.b = 0x00U, .d = 0x13U, .f =0x5U}, +const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM] = { + {VMSIX_ON_MSI_DEV0}, + {VMSIX_ON_MSI_DEV1}, + {VMSIX_ON_MSI_DEV2}, + {VMSIX_ON_MSI_DEV3}, + {VMSIX_ON_MSI_DEV4}, +}; diff --git a/misc/config_tools/data/generic_board/generic_code/boards/board_info.h b/misc/config_tools/data/generic_board/generic_code/boards/board_info.h new file mode 100644 index 000000000..6b7ad0087 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/boards/board_info.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_INFO_H +#define BOARD_INFO_H + +#define MAX_PCPU_NUM 4U +#define MAX_VMSIX_ON_MSI_PDEVS_NUM 5U +#define MAX_HIDDEN_PDEVS_NUM 0U + +#define HI_MMIO_START ~0UL +#define HI_MMIO_END 0UL +#define HI_MMIO_SIZE 0x10000000UL + +#endif /* BOARD_INFO_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/boards/pci_devices.h b/misc/config_tools/data/generic_board/generic_code/boards/pci_devices.h new file mode 100644 index 000000000..b4bb1bf95 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/boards/pci_devices.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: Intel Corporation + * Version: EHLSFWI1.R00.2224.A00.2005281500 + * Release Date: 05/28/2020 + * + * Base Board Information + * Manufacturer: Intel Corporation + * Product Name: ElkhartLake LPDDR4x T3 CRB + * Version: 2 + */ + +#ifndef PCI_DEVICES_H_ +#define PCI_DEVICES_H_ + +#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U} + +#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U} + +#define SYSTEM_PERIPHERAL_0 .pbdf.bits = {.b = 0x00U, .d = 0x08U, .f = 0x00U} + +#define SYSTEM_PERIPHERAL_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x10U, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x10U, .f = 0x01U} + +#define SERIAL_BUS_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_4 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x02U} + +#define SERIAL_BUS_CONTROLLER_5 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x03U} + +#define SERIAL_BUS_CONTROLLER_6 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_7 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_8 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x01U} + +#define SERIAL_BUS_CONTROLLER_9 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x06U} + +#define SERIAL_BUS_CONTROLLER_10 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U} + +#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x04U} + +#define COMMUNICATION_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x05U} + +#define COMMUNICATION_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U} + +#define COMMUNICATION_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x02U} + +#define COMMUNICATION_CONTROLLER_4 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U} + +#define COMMUNICATION_CONTROLLER_5 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x01U} + +#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U} + +#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U} + +#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U} + +#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U} + +#define SD_HOST_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x01U} + +#define NON_VGA_UNCLASSIFIED_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x03U} + +#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U} + +#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U} + +#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x02U} + +#define ETHERNET_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x04U} + +#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U} + +#define MULTIMEDIA_AUDIO_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U} + +#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U} + +#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U} + +#endif /* PCI_DEVICES_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/boards/platform_acpi_info.h b/misc/config_tools/data/generic_board/generic_code/boards/platform_acpi_info.h new file mode 100644 index 000000000..d660f91aa --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/boards/platform_acpi_info.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING! + */ + +#ifndef PLATFORM_ACPI_INFO_H +#define PLATFORM_ACPI_INFO_H + +/* + * BIOS Information + * Vendor: Intel Corporation + * Version: EHLSFWI1.R00.2224.A00.2005281500 + * Release Date: 05/28/2020 + * + * Base Board Information + * Manufacturer: Intel Corporation + * Product Name: ElkhartLake LPDDR4x T3 CRB + * Version: 2 + */ + +/* pm sstate data */ +#define PM1A_EVT_ADDRESS 0x1800UL +#define PM1A_EVT_ACCESS_SIZE 0x2U +#define PM1A_CNT_ADDRESS 0x1804UL + +#define WAKE_VECTOR_32 0x66BB000CUL +#define WAKE_VECTOR_64 0x66BB0018UL + +#define RESET_REGISTER_ADDRESS 0xCF9UL +#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO +#define RESET_REGISTER_VALUE 0x6U + +/* DRHD of DMAR */ +#define DRHD_COUNT 3U + +#define DRHD0_DEV_CNT 0x1U +#define DRHD0_SEGMENT 0x0U +#define DRHD0_FLAGS 0x0U +#define DRHD0_REG_BASE 0xFED90000UL +#define DRHD0_IGNORE true +#define DRHD0_DEVSCOPE0_TYPE 0x1U +#define DRHD0_DEVSCOPE0_ID 0x0U +#define DRHD0_DEVSCOPE0_BUS 0x0U +#define DRHD0_DEVSCOPE0_PATH 0x10U + +#define DRHD1_DEV_CNT 0x2U +#define DRHD1_SEGMENT 0x0U +#define DRHD1_FLAGS 0x1U +#define DRHD1_REG_BASE 0xFED91000UL +#define DRHD1_IGNORE false +#define DRHD1_DEVSCOPE0_TYPE 0x3U +#define DRHD1_DEVSCOPE0_ID 0x2U +#define DRHD1_DEVSCOPE0_BUS 0x0U +#define DRHD1_DEVSCOPE0_PATH 0xf7U +#define DRHD1_DEVSCOPE1_TYPE 0x4U +#define DRHD1_DEVSCOPE1_ID 0x0U +#define DRHD1_DEVSCOPE1_BUS 0x0U +#define DRHD1_DEVSCOPE1_PATH 0xf6U + +#define DRHD2_DEV_CNT 0x3U +#define DRHD2_SEGMENT 0x0U +#define DRHD2_FLAGS 0x0U +#define DRHD2_REG_BASE 0x00UL +#define DRHD2_IGNORE false +#define DRHD2_DEVSCOPE0_TYPE 0x5U +#define DRHD2_DEVSCOPE0_ID 0x3U +#define DRHD2_DEVSCOPE0_BUS 0x0U +#define DRHD2_DEVSCOPE0_PATH 0xebU +#define DRHD2_DEVSCOPE1_TYPE 0x5U +#define DRHD2_DEVSCOPE1_ID 0x4U +#define DRHD2_DEVSCOPE1_BUS 0x0U +#define DRHD2_DEVSCOPE1_PATH 0xecU +#define DRHD2_DEVSCOPE2_TYPE 0x5U +#define DRHD2_DEVSCOPE2_ID 0x5U +#define DRHD2_DEVSCOPE2_BUS 0x0U +#define DRHD2_DEVSCOPE2_PATH 0xedU + +/* PCI mmcfg base of MCFG */ +#define DEFAULT_PCI_MMCFG_BASE 0xc0000000UL + +/* PCI mmcfg bus number of MCFG */ +#define DEFAULT_PCI_MMCFG_START_BUS 0x0U +#define DEFAULT_PCI_MMCFG_END_BUS 0xFFU + + +#endif /* PLATFORM_ACPI_INFO_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/apic.asl b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/apic.asl new file mode 100644 index 000000000..25b1ab60f --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/apic.asl @@ -0,0 +1,46 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[0004] Table Length : 0000004E +[0001] Revision : 03 +[0001] Checksum : 9B +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Local Apic Address : FEE00000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[0001] Subtable Type : 01 [I/O APIC] +[0001] Length : 0C +[0001] I/O Apic ID : 01 +[0001] Reserved : 00 +[0004] Address : FEC00000 +[0004] Interrupt : 00000000 + +[0001] Subtable Type : 04 [Local APIC NMI] +[0001] Length : 06 +[0001] Processor ID : FF +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] Interrupt Input LINT : 01 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Local Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/dsdt.asl b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/dsdt.asl new file mode 100644 index 000000000..f72e7567e --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/dsdt.asl @@ -0,0 +1,25 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00000051 (81) + * Revision 0x03 + * Checksum 0xF0 + * OEM ID "ACRN " + * OEM Table ID "ACRNDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "INTL" + * Compiler Version 0x20190703 (538511107) + */ +DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001) +{ + Name (_S5, Package () + { + 0x05, + Zero, + }) +} + diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/facp.asl b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/facp.asl new file mode 100644 index 000000000..74565174c --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/facp.asl @@ -0,0 +1,170 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 00 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNFADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 7FF00240 +[0001] Model : 00 +[0001] PM Profile : 00 [Unspecified] +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000000 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000000 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000000 +[0004] PM Timer Block Address : 00000000 +[0004] GPE0 Block Address : 00000000 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 00 +[0001] PM1 Control Block Length : 00 +[0001] PM2 Control Block Length : 00 +[0001] PM Timer Block Length : 00 +[0001] GPE0 Block Length : 00 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 1 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 +Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000CF9 + +[0001] Value to cause reset : 0E +[0002] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[0001] FADT Minor Revision : 00 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000000 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000400 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000401 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/mcfg.asl b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/mcfg.asl new file mode 100644 index 000000000..1d4de63bc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/mcfg.asl @@ -0,0 +1,27 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "MCFG" [Memory Mapped Configuration table] +[0004] Table Length : 0000003C +[0001] Revision : 03 +[0001] Checksum : A5 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMCFG" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 00000000E0000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : FF +[0004] Reserved : 00000000 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/rsdp.asl b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/rsdp.asl new file mode 100644 index 000000000..0dacd86e9 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/rsdp.asl @@ -0,0 +1,16 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Template for [RSDP] ACPI Table (AML byte code table) + */ +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "ACRN " +[0001] Revision : 02 +[0004] RSDT Address : 0000000000000000 +[0004] Length : 00000024 +[0008] XSDT Address : 000000007FF00080 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/xsdt.asl b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/xsdt.asl new file mode 100644 index 000000000..71e92a970 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/xsdt.asl @@ -0,0 +1,23 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [XSDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "XSDT" [Extended System Description Table] +[0004] Table Length : 00000044 +[0001] Revision : 01 +[0001] Checksum : 75 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNXSDT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] ACPI Table Address 0 : 000000007FF00100 +[0008] ACPI Table Address 1 : 000000007FF00440 +[0008] ACPI Table Address 2 : 000000007FF00480 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/generic_board.config b/misc/config_tools/data/generic_board/generic_code/hybrid/generic_board.config new file mode 100644 index 000000000..ed99cee9d --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/generic_board.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="generic_board" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x9600000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_IVSHMEM_ENABLED=n +CONFIG_GPU_SBDF=0x00000010 +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=256 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_PCI=y +CONFIG_SERIAL_PCI_BDF=0xca +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h new file mode 100644 index 000000000..05426ddcc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef IVSHMEM_CFG_H +#define IVSHMEM_CFG_H + +#endif /* IVSHMEM_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h new file mode 100644 index 000000000..6a244f6d3 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/sda3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 5U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "swiotlb=131072 " \ + "maxcpus=3" + +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U)) + +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) + +#ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ +#define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ +#define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U + +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU + +#define VM0_VCPU_CLOS {0U} +#define VM1_VCPU_CLOS {0U, 0U, 0U} +#define VM2_VCPU_CLOS {0U} +#endif + + +#define VM0_BOOT_ARGS "reboot=acpi" + + +#define VM0_PT_INTX_NUM 0U + +#endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c new file mode 100644 index 000000000..3ae881679 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c new file mode 100644 index 000000000..021123bb1 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +struct pt_intx_config vm0_pt_intx[1U]; + diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h new file mode 100644 index 000000000..c885dca39 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ + .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL + +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL + +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL + +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL + +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL + +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL + +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL + +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL + +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL + +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL + +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL + +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL + +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ + .vbar_base[1] = 0x80000000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL + +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL + +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL + +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL + +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL + +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ + .vbar_base[2] = 0x834e7000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ + .vbar_base[1] = 0x834f6000UL, \ + .vbar_base[5] = 0x834f5000UL + +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL + +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL + +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL + +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ + .vbar_base[2] = 0x834f2000UL + +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ + .vbar_base[4] = 0x83200000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c new file mode 100644 index 000000000..647e7dff0 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include + +extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; + +extern struct pt_intx_config vm0_pt_intx[1U]; + +struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { + { /* VM0 */ + CONFIG_SAFETY_VM(1), + .name = "ACRN PRE-LAUNCHED VM0", + .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, + .guest_flags = 0UL, +#ifdef CONFIG_RDT_ENABLED + .clos = VM0_VCPU_CLOS, +#endif + .memory = { + .start_hpa = VM0_CONFIG_MEM_START_HPA, + .size = VM0_CONFIG_MEM_SIZE, + .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = { + .name = "Zephyr", + .kernel_type = KERNEL_ZEPHYR, + .kernel_mod_tag = "Zephyr_RawImage", + .kernel_load_addr = 0x8000, + .kernel_entry_addr = 0x8000, + .bootargs = VM0_BOOT_ARGS, + }, + .acpi_config = { + .acpi_mod_tag = "ACPI_VM0", + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 1U, + .t_vuart.vuart_id = 1U, + }, +#ifdef VM0_PASSTHROUGH_TPM + .pt_tpm2 = true, + .mmiodevs[0] = { + .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, + .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, + .size = VM0_TPM_BUFFER_SIZE, + }, +#endif +#ifdef P2SB_BAR_ADDR + .pt_p2sb_bar = true, + .mmiodevs[0] = { + .base_gpa = P2SB_BAR_ADDR_GPA, + .base_hpa = P2SB_BAR_ADDR, + .size = P2SB_BAR_SIZE, + }, +#endif + .pt_intx_num = VM0_PT_INTX_NUM, + .pt_intx = &vm0_pt_intx[0U], + }, + { /* VM1 */ + CONFIG_SOS_VM, + .name = "ACRN SOS VM", + + /* Allow SOS to reboot the host since there is supposed to be the highest severity guest */ + .guest_flags = 0UL, +#ifdef CONFIG_RDT_ENABLED + .clos = VM1_VCPU_CLOS, +#endif + .cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY, + .memory = { + .start_hpa = 0UL, + .size = CONFIG_SOS_RAM_SIZE, + }, + .os_config = { + .name = "ACRN Service OS", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = SOS_VM_BOOTARGS, + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM1_BASE, + .irq = SOS_COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM2_BASE, + .irq = SOS_COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, + .pci_dev_num = 0U, + .pci_devs = sos_pci_devs, + }, + { /* VM2 */ + CONFIG_POST_STD_VM(1), +#ifdef CONFIG_RDT_ENABLED + .clos = VM2_VCPU_CLOS, +#endif + .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, +}; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h new file mode 100644 index 000000000..62017c7b7 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef VM_CONFIGURATIONS_H +#define VM_CONFIGURATIONS_H + +#include +#include + +/* SOS_VM_NUM can only be 0U or 1U; + * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; + * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; + */ +#define PRE_VM_NUM 1U +#define SOS_VM_NUM 1U +#define MAX_POST_VM_NUM 1U +#define CONFIG_MAX_KATA_VM_NUM 0U + +/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ +#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ + GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) + +#define VM0_CONFIG_MEM_START_HPA 0x100000000UL +#define VM0_CONFIG_MEM_SIZE 0x20000000UL +#define VM0_CONFIG_MEM_START_HPA2 0x0UL +#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL + +/* SOS_VM == VM1 */ +#define SOS_VM_BOOTARGS SOS_ROOTFS \ + SOS_CONSOLE \ + SOS_IDLE \ + SOS_BOOTARGS_DIFF + +#endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/apic.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/apic.asl new file mode 100644 index 000000000..84bb878fd --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/apic.asl @@ -0,0 +1,54 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[0004] Table Length : 0000004E +[0001] Revision : 03 +[0001] Checksum : 9B +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Local Apic Address : FEE00000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[0001] Subtable Type : 01 [I/O APIC] +[0001] Length : 0C +[0001] I/O Apic ID : 01 +[0001] Reserved : 00 +[0004] Address : FEC00000 +[0004] Interrupt : 00000000 + +[0001] Subtable Type : 04 [Local APIC NMI] +[0001] Length : 06 +[0001] Processor ID : FF +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] Interrupt Input LINT : 01 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Local Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 01 +[0001] Local Apic ID : 01 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/dsdt.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/dsdt.asl new file mode 100644 index 000000000..518dff7a4 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/dsdt.asl @@ -0,0 +1,81 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00000051 (81) + * Revision 0x03 + * Checksum 0xF0 + * OEM ID "ACRN " + * OEM Table ID "ACRNDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "INTL" + * Compiler Version 0x20190703 (538511107) + */ +DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001) +{ + Scope (_SB) + { + Device (OTN1) + { + Name (_ADR, 0x00020000) // _ADR: Address + OperationRegion (TSRT, PCI_Config, Zero, 0x0100) + Field (TSRT, AnyAcc, NoLock, Preserve) + { + DVID, 16, + Offset (0x10), + TADL, 32, + TADH, 32 + } + } + + Device (PCS2) + { + Name (_HID, "INTC1033") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (PCSR, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000004, // Address Length + _Y00) + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000004, // Address Length + _Y01) + }) + CreateDWordField (PCSR, \_SB.PCS2._CRS._Y00._BAS, MAL0) // _BAS: Base Address + MAL0 = ((^^OTN1.TADL & 0xFFFFF000) + 0x0200) + CreateDWordField (PCSR, \_SB.PCS2._CRS._Y01._BAS, MDL0) // _BAS: Base Address + MDL0 = ((^^OTN1.TADL & 0xFFFFF000) + 0x0204) + Return (PCSR) /* \_SB_.PCS2._CRS.PCSR */ + } + } + } + Device (TPM) + { + Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + } + Name (_S5, Package () + { + 0x05, + Zero, + }) +} + diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/facp.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/facp.asl new file mode 100644 index 000000000..74565174c --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/facp.asl @@ -0,0 +1,170 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 00 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNFADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 7FF00240 +[0001] Model : 00 +[0001] PM Profile : 00 [Unspecified] +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000000 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000000 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000000 +[0004] PM Timer Block Address : 00000000 +[0004] GPE0 Block Address : 00000000 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 00 +[0001] PM1 Control Block Length : 00 +[0001] PM2 Control Block Length : 00 +[0001] PM Timer Block Length : 00 +[0001] GPE0 Block Length : 00 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 1 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 +Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000CF9 + +[0001] Value to cause reset : 0E +[0002] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[0001] FADT Minor Revision : 00 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000000 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000400 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000401 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/mcfg.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/mcfg.asl new file mode 100644 index 000000000..1d4de63bc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/mcfg.asl @@ -0,0 +1,27 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "MCFG" [Memory Mapped Configuration table] +[0004] Table Length : 0000003C +[0001] Revision : 03 +[0001] Checksum : A5 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMCFG" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 00000000E0000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : FF +[0004] Reserved : 00000000 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/rsdp.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/rsdp.asl new file mode 100644 index 000000000..0dacd86e9 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/rsdp.asl @@ -0,0 +1,16 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Template for [RSDP] ACPI Table (AML byte code table) + */ +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "ACRN " +[0001] Revision : 02 +[0004] RSDT Address : 0000000000000000 +[0004] Length : 00000024 +[0008] XSDT Address : 000000007FF00080 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/tpm2.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/tpm2.asl new file mode 100644 index 000000000..2a2a08fc8 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/tpm2.asl @@ -0,0 +1,23 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [TPM2] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[0004] Table Length : 00000034 +[0001] Revision : 03 +[0001] Checksum : 67 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNTPM2" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Reserved : 00000000 +[0008] Control Address : 00000000FED40040 +[0004] Start Method : 07 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/xsdt.asl b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/xsdt.asl new file mode 100644 index 000000000..72a586479 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ACPI_VM0/xsdt.asl @@ -0,0 +1,24 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [XSDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "XSDT" [Extended System Description Table] +[0004] Table Length : 00000044 +[0001] Revision : 01 +[0001] Checksum : 75 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNXSDT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] ACPI Table Address 0 : 000000007FF00100 +[0008] ACPI Table Address 1 : 000000007FF00440 +[0008] ACPI Table Address 2 : 000000007FF00480 +[0008] ACPI Table Address 3 : 000000007FF01100 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/generic_board.config b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/generic_board.config new file mode 100644 index 000000000..4c1b57aa2 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/generic_board.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="generic_board" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0xc000000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_IVSHMEM_ENABLED=y +CONFIG_GPU_SBDF=0x00000010 +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=256 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_PCI=y +CONFIG_SERIAL_PCI_BDF=0xca +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h new file mode 100644 index 000000000..e5e2c2a7e --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef IVSHMEM_CFG_H +#define IVSHMEM_CFG_H + +#include +#include + +#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0" + +/* + * The IVSHMEM_SHM_SIZE is the sum of all memory regions. + * The size range of each memory region is [2MB, 512MB] and is a power of 2. + */ +#define IVSHMEM_SHM_SIZE 0x200000UL +#define IVSHMEM_DEV_NUM 2UL + +/* All user defined memory regions */ +#define IVSHMEM_SHM_REGIONS \ + { \ + .name = IVSHMEM_SHM_REGION_0, \ + .size = 0x200000UL, /* 2M */ \ + }, + +#endif /* IVSHMEM_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h new file mode 100644 index 000000000..d74ec2679 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/nvme0n1p3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 5U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "swiotlb=131072 " \ + "maxcpus=2" + +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) + +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) + +#ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ +#define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ +#define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U + +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU + +#define VM0_VCPU_CLOS {0U, 0U} +#define VM1_VCPU_CLOS {0U, 0U} +#define VM2_VCPU_CLOS {0U, 0U} +#define VM3_VCPU_CLOS {0U} +#endif + +#define VM0_CONFIG_PCI_DEV_NUM 4U +#define VM2_CONFIG_PCI_DEV_NUM 1U + +#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 no_ipi_broadcast=1 \ +console=ttyS0 noxsave nohpet no_timer_check \ +ignore_loglevel consoleblank=0 tsc=reliable clocksource=tsc \ +x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 intel_pstate=disable \ +mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 \ +rcu_nocbs=1 nosoftlockup idle=poll irqaffinity=0 \ +reboot=acpi" + + +#define VM0_PT_INTX_NUM 0U + +#endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c new file mode 100644 index 000000000..be1c09a8f --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for + * passthrough device configuration and shm_name for ivshmem device configuration. + */ +#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR + +/* + * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops + * to simplify the code. + */ + +struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = { + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}, + .vdev_ops = &vhostbridge_ops, + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U}, + PTDEV(SATA_CONTROLLER_0), + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, + PTDEV(ETHERNET_CONTROLLER_1), + }, + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U}, + .vdev_ops = &vpci_ivshmem_ops, + .shm_region_name = IVSHMEM_SHM_REGION_0, + IVSHMEM_DEVICE_0_VBAR + }, +}; + +struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; + +struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = { + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.value = UNASSIGNED_VBDF, + .vdev_ops = &vpci_ivshmem_ops, + .shm_region_name = IVSHMEM_SHM_REGION_0 + }, +}; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c new file mode 100644 index 000000000..021123bb1 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +struct pt_intx_config vm0_pt_intx[1U]; + diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h new file mode 100644 index 000000000..bec26d166 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, \ + .vbar_base[1] = 0x80001000UL, \ + .vbar_base[2] = 0x8020000cUL + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ + .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL + +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL + +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL + +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL + +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL + +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL + +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL + +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL + +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL + +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL + +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL + +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL + +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ + .vbar_base[1] = 0x80000000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL + +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL + +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL + +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL + +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL + +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ + .vbar_base[2] = 0x834e7000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ + .vbar_base[1] = 0x834f6000UL, \ + .vbar_base[5] = 0x834f5000UL + +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL + +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL + +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL, \ + .vbar_base[2] = 0x80002000UL + +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ + .vbar_base[2] = 0x834f2000UL + +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ + .vbar_base[4] = 0x83200000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c new file mode 100644 index 000000000..8ea49a44b --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include + +extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM]; +extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; +extern struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM]; + +extern struct pt_intx_config vm0_pt_intx[1U]; + +struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { + { /* VM0 */ + CONFIG_PRE_RT_VM(1), + .name = "ACRN PRE-LAUNCHED VM0", + .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, + .guest_flags = (GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT), +#ifdef CONFIG_RDT_ENABLED + .clos = VM0_VCPU_CLOS, +#endif + .memory = { + .start_hpa = VM0_CONFIG_MEM_START_HPA, + .size = VM0_CONFIG_MEM_SIZE, + .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = { + .name = "PREEMPT-RT", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "RT_bzImage", + .bootargs = VM0_BOOT_ARGS, + }, + .acpi_config = { + .acpi_mod_tag = "ACPI_VM0", + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 1U, + .t_vuart.vuart_id = 1U, + }, + .pci_dev_num = VM0_CONFIG_PCI_DEV_NUM, + .pci_devs = vm0_pci_devs, +#ifdef VM0_PASSTHROUGH_TPM + .pt_tpm2 = true, + .mmiodevs[0] = { + .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, + .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, + .size = VM0_TPM_BUFFER_SIZE, + }, +#endif +#ifdef P2SB_BAR_ADDR + .pt_p2sb_bar = true, + .mmiodevs[0] = { + .base_gpa = P2SB_BAR_ADDR_GPA, + .base_hpa = P2SB_BAR_ADDR, + .size = P2SB_BAR_SIZE, + }, +#endif + .pt_intx_num = VM0_PT_INTX_NUM, + .pt_intx = &vm0_pt_intx[0U], + }, + { /* VM1 */ + CONFIG_SOS_VM, + .name = "ACRN SOS VM", + + /* Allow SOS to reboot the host since there is supposed to be the highest severity guest */ + .guest_flags = 0UL, +#ifdef CONFIG_RDT_ENABLED + .clos = VM1_VCPU_CLOS, +#endif + .cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY, + .memory = { + .start_hpa = 0UL, + .size = CONFIG_SOS_RAM_SIZE, + }, + .os_config = { + .name = "ACRN Service OS", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = SOS_VM_BOOTARGS, + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM1_BASE, + .irq = SOS_COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM2_BASE, + .irq = SOS_COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, + .pci_dev_num = 0U, + .pci_devs = sos_pci_devs, + }, + { /* VM2 */ + CONFIG_POST_STD_VM(1), +#ifdef CONFIG_RDT_ENABLED + .clos = VM2_VCPU_CLOS, +#endif + /* The PCI device configuration is only for in-hypervisor vPCI devices. */ + .pci_dev_num = VM2_CONFIG_PCI_DEV_NUM, + .pci_devs = vm2_pci_devs, + .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, + { /* VM3 */ + CONFIG_POST_STD_VM(2), +#ifdef CONFIG_RDT_ENABLED + .clos = VM3_VCPU_CLOS, +#endif + .cpu_affinity = VM3_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, +}; diff --git a/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h new file mode 100644 index 000000000..a2c3758bf --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef VM_CONFIGURATIONS_H +#define VM_CONFIGURATIONS_H + +#include +#include + +/* SOS_VM_NUM can only be 0U or 1U; + * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; + * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; + */ +#define PRE_VM_NUM 1U +#define SOS_VM_NUM 1U +#define MAX_POST_VM_NUM 2U +#define CONFIG_MAX_KATA_VM_NUM 0U + +/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ +#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ + GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) + +#define VM0_CONFIG_MEM_START_HPA 0x100000000UL +#define VM0_CONFIG_MEM_SIZE 0x40000000UL +#define VM0_CONFIG_MEM_START_HPA2 0x0UL +#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL + +/* SOS_VM == VM1 */ +#define SOS_VM_BOOTARGS SOS_ROOTFS \ + SOS_CONSOLE \ + SOS_IDLE \ + SOS_BOOTARGS_DIFF + +#endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/generic_board.config b/misc/config_tools/data/generic_board/generic_code/industry/generic_board.config new file mode 100644 index 000000000..4c83090a3 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/generic_board.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="generic_board" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x14800000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_IVSHMEM_ENABLED=n +CONFIG_GPU_SBDF=0x00000010 +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=y +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=256 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_MMIO=y +CONFIG_SERIAL_MMIO_BASE=0xfe042000 +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h new file mode 100644 index 000000000..05426ddcc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef IVSHMEM_CFG_H +#define IVSHMEM_CFG_H + +#endif /* IVSHMEM_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h new file mode 100644 index 000000000..fe86a6633 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/nvme0n1p3 " +#define SOS_CONSOLE "console=ttyS3 " +#define SOS_COM1_BASE 0x2E8U +#define SOS_COM1_IRQ 3U +#define SOS_COM2_BASE 0x3F8U +#define SOS_COM2_IRQ 4U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "swiotlb=131072 " \ + "maxcpus=4" + + +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) +#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) +#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) + +#ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ +#define HV_SUPPORTED_MAX_CLOS 16U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ +#define MAX_MBA_CLOS_NUM_ENTRIES 16U + +/* Max number of MBA delay entries corresponding to each CLOS. */ +#define MAX_CACHE_CLOS_NUM_ENTRIES 16U + +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU + +#define VM0_VCPU_CLOS {0U} +#define VM1_VCPU_CLOS {0U, 0U} +#define VM2_VCPU_CLOS {0U, 0U} +#define VM3_VCPU_CLOS {0U, 0U} +#define VM4_VCPU_CLOS {0U, 0U} +#define VM5_VCPU_CLOS {0U, 0U} +#define VM6_VCPU_CLOS {0U, 0U} +#define VM7_VCPU_CLOS {0U, 0U} +#endif + + + +#define VM0_PT_INTX_NUM 0U + +#endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c new file mode 100644 index 000000000..3ae881679 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; diff --git a/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c new file mode 100644 index 000000000..021123bb1 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +struct pt_intx_config vm0_pt_intx[1U]; + diff --git a/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h new file mode 100644 index 000000000..c885dca39 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ + .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL + +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL + +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL + +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL + +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL + +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL + +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL + +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL + +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL + +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL + +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL + +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL + +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ + .vbar_base[1] = 0x80000000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL + +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL + +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL + +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL + +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL + +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ + .vbar_base[2] = 0x834e7000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ + .vbar_base[1] = 0x834f6000UL, \ + .vbar_base[5] = 0x834f5000UL + +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL + +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL + +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL + +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ + .vbar_base[2] = 0x834f2000UL + +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ + .vbar_base[4] = 0x83200000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c new file mode 100644 index 000000000..0ddfadc78 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include + +extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; + +extern struct pt_intx_config vm0_pt_intx[1U]; + +struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { + { /* VM0 */ + CONFIG_SOS_VM, + .name = "ACRN SOS VM", + + /* Allow SOS to reboot the host since there is supposed to be the highest severity guest */ + .guest_flags = 0UL, +#ifdef CONFIG_RDT_ENABLED + .clos = VM0_VCPU_CLOS, +#endif + .cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY, + .memory = { + .start_hpa = 0UL, + .size = CONFIG_SOS_RAM_SIZE, + }, + .os_config = { + .name = "ACRN Service OS", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = SOS_VM_BOOTARGS, + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM1_BASE, + .irq = SOS_COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = SOS_COM2_BASE, + .irq = SOS_COM2_IRQ, + .t_vuart.vm_id = 2U, + .t_vuart.vuart_id = 1U, + }, + .pci_dev_num = 0U, + .pci_devs = sos_pci_devs, + }, + { /* VM1 */ + CONFIG_POST_STD_VM(1), +#ifdef CONFIG_RDT_ENABLED + .clos = VM1_VCPU_CLOS, +#endif + .cpu_affinity = VM1_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, + { /* VM2 */ + CONFIG_POST_RT_VM(1), +#ifdef CONFIG_RDT_ENABLED + .clos = VM2_VCPU_CLOS, +#endif + .cpu_affinity = VM2_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, + }, + { /* VM3 */ + CONFIG_POST_STD_VM(2), +#ifdef CONFIG_RDT_ENABLED + .clos = VM3_VCPU_CLOS, +#endif + .cpu_affinity = VM3_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, + { /* VM4 */ + CONFIG_POST_STD_VM(3), +#ifdef CONFIG_RDT_ENABLED + .clos = VM4_VCPU_CLOS, +#endif + .cpu_affinity = VM4_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, + { /* VM5 */ + CONFIG_POST_STD_VM(4), +#ifdef CONFIG_RDT_ENABLED + .clos = VM5_VCPU_CLOS, +#endif + .cpu_affinity = VM5_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, + { /* VM6 */ + CONFIG_POST_STD_VM(5), +#ifdef CONFIG_RDT_ENABLED + .clos = VM6_VCPU_CLOS, +#endif + .cpu_affinity = VM6_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, + { /* VM7 */ + CONFIG_KATA_VM(1), +#ifdef CONFIG_RDT_ENABLED + .clos = VM7_VCPU_CLOS, +#endif + .cpu_affinity = VM7_CONFIG_CPU_AFFINITY, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = INVALID_COM_BASE, + }, + }, +}; diff --git a/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h new file mode 100644 index 000000000..a9a63a3f7 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef VM_CONFIGURATIONS_H +#define VM_CONFIGURATIONS_H + +#include +#include + +/* SOS_VM_NUM can only be 0U or 1U; + * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; + * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; + */ +#define PRE_VM_NUM 0U +#define SOS_VM_NUM 1U +#define MAX_POST_VM_NUM 7U +#define CONFIG_MAX_KATA_VM_NUM 1U + +/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ +#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ + GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) + +/* SOS_VM == VM0 */ +#define SOS_VM_BOOTARGS SOS_ROOTFS \ + SOS_CONSOLE \ + SOS_IDLE \ + SOS_BOOTARGS_DIFF + +#endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/apic.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/apic.asl new file mode 100644 index 000000000..84bb878fd --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/apic.asl @@ -0,0 +1,54 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[0004] Table Length : 0000004E +[0001] Revision : 03 +[0001] Checksum : 9B +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Local Apic Address : FEE00000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[0001] Subtable Type : 01 [I/O APIC] +[0001] Length : 0C +[0001] I/O Apic ID : 01 +[0001] Reserved : 00 +[0004] Address : FEC00000 +[0004] Interrupt : 00000000 + +[0001] Subtable Type : 04 [Local APIC NMI] +[0001] Length : 06 +[0001] Processor ID : FF +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] Interrupt Input LINT : 01 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Local Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 01 +[0001] Local Apic ID : 01 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/dsdt.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/dsdt.asl new file mode 100644 index 000000000..f72e7567e --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/dsdt.asl @@ -0,0 +1,25 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00000051 (81) + * Revision 0x03 + * Checksum 0xF0 + * OEM ID "ACRN " + * OEM Table ID "ACRNDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "INTL" + * Compiler Version 0x20190703 (538511107) + */ +DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001) +{ + Name (_S5, Package () + { + 0x05, + Zero, + }) +} + diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/facp.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/facp.asl new file mode 100644 index 000000000..74565174c --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/facp.asl @@ -0,0 +1,170 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 00 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNFADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 7FF00240 +[0001] Model : 00 +[0001] PM Profile : 00 [Unspecified] +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000000 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000000 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000000 +[0004] PM Timer Block Address : 00000000 +[0004] GPE0 Block Address : 00000000 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 00 +[0001] PM1 Control Block Length : 00 +[0001] PM2 Control Block Length : 00 +[0001] PM Timer Block Length : 00 +[0001] GPE0 Block Length : 00 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 1 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 +Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000CF9 + +[0001] Value to cause reset : 0E +[0002] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[0001] FADT Minor Revision : 00 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000000 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000400 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000401 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/mcfg.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/mcfg.asl new file mode 100644 index 000000000..1d4de63bc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/mcfg.asl @@ -0,0 +1,27 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "MCFG" [Memory Mapped Configuration table] +[0004] Table Length : 0000003C +[0001] Revision : 03 +[0001] Checksum : A5 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMCFG" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 00000000E0000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : FF +[0004] Reserved : 00000000 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/rsdp.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/rsdp.asl new file mode 100644 index 000000000..0dacd86e9 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/rsdp.asl @@ -0,0 +1,16 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Template for [RSDP] ACPI Table (AML byte code table) + */ +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "ACRN " +[0001] Revision : 02 +[0004] RSDT Address : 0000000000000000 +[0004] Length : 00000024 +[0008] XSDT Address : 000000007FF00080 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/xsdt.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/xsdt.asl new file mode 100644 index 000000000..71e92a970 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM0/xsdt.asl @@ -0,0 +1,23 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [XSDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "XSDT" [Extended System Description Table] +[0004] Table Length : 00000044 +[0001] Revision : 01 +[0001] Checksum : 75 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNXSDT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] ACPI Table Address 0 : 000000007FF00100 +[0008] ACPI Table Address 1 : 000000007FF00440 +[0008] ACPI Table Address 2 : 000000007FF00480 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/apic.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/apic.asl new file mode 100644 index 000000000..84bb878fd --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/apic.asl @@ -0,0 +1,54 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[0004] Table Length : 0000004E +[0001] Revision : 03 +[0001] Checksum : 9B +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Local Apic Address : FEE00000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[0001] Subtable Type : 01 [I/O APIC] +[0001] Length : 0C +[0001] I/O Apic ID : 01 +[0001] Reserved : 00 +[0004] Address : FEC00000 +[0004] Interrupt : 00000000 + +[0001] Subtable Type : 04 [Local APIC NMI] +[0001] Length : 06 +[0001] Processor ID : FF +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] Interrupt Input LINT : 01 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Local Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 01 +[0001] Local Apic ID : 01 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/dsdt.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/dsdt.asl new file mode 100644 index 000000000..f72e7567e --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/dsdt.asl @@ -0,0 +1,25 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00000051 (81) + * Revision 0x03 + * Checksum 0xF0 + * OEM ID "ACRN " + * OEM Table ID "ACRNDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "INTL" + * Compiler Version 0x20190703 (538511107) + */ +DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001) +{ + Name (_S5, Package () + { + 0x05, + Zero, + }) +} + diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/facp.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/facp.asl new file mode 100644 index 000000000..74565174c --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/facp.asl @@ -0,0 +1,170 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 00 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNFADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 7FF00240 +[0001] Model : 00 +[0001] PM Profile : 00 [Unspecified] +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000000 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000000 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000000 +[0004] PM Timer Block Address : 00000000 +[0004] GPE0 Block Address : 00000000 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 00 +[0001] PM1 Control Block Length : 00 +[0001] PM2 Control Block Length : 00 +[0001] PM Timer Block Length : 00 +[0001] GPE0 Block Length : 00 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 1 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 +Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000CF9 + +[0001] Value to cause reset : 0E +[0002] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[0001] FADT Minor Revision : 00 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000000 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000400 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000401 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/mcfg.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/mcfg.asl new file mode 100644 index 000000000..1d4de63bc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/mcfg.asl @@ -0,0 +1,27 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "MCFG" [Memory Mapped Configuration table] +[0004] Table Length : 0000003C +[0001] Revision : 03 +[0001] Checksum : A5 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMCFG" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 00000000E0000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : FF +[0004] Reserved : 00000000 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/rsdp.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/rsdp.asl new file mode 100644 index 000000000..0dacd86e9 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/rsdp.asl @@ -0,0 +1,16 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Template for [RSDP] ACPI Table (AML byte code table) + */ +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "ACRN " +[0001] Revision : 02 +[0004] RSDT Address : 0000000000000000 +[0004] Length : 00000024 +[0008] XSDT Address : 000000007FF00080 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/xsdt.asl b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/xsdt.asl new file mode 100644 index 000000000..71e92a970 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ACPI_VM1/xsdt.asl @@ -0,0 +1,23 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [XSDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "XSDT" [Extended System Description Table] +[0004] Table Length : 00000044 +[0001] Revision : 01 +[0001] Checksum : 75 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNXSDT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] ACPI Table Address 0 : 000000007FF00100 +[0008] ACPI Table Address 1 : 000000007FF00440 +[0008] ACPI Table Address 2 : 000000007FF00480 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/generic_board.config b/misc/config_tools/data/generic_board/generic_code/logical_partition/generic_board.config new file mode 100644 index 000000000..cfc37d499 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/generic_board.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="generic_board" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x7800000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_IVSHMEM_ENABLED=n +CONFIG_GPU_SBDF=0x00000010 +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=64 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_PCI=y +CONFIG_SERIAL_PCI_BDF=0xca +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h new file mode 100644 index 000000000..05426ddcc --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef IVSHMEM_CFG_H +#define IVSHMEM_CFG_H + +#endif /* IVSHMEM_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h new file mode 100644 index 000000000..6a2732e95 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U)) +#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U)) + +#ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ +#define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ +#define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U + +#define CLOS_MASK_0 0xfffU +#define CLOS_MASK_1 0xfffU +#define CLOS_MASK_2 0xfffU +#define CLOS_MASK_3 0xfffU +#define CLOS_MASK_4 0xfffU +#define CLOS_MASK_5 0xfffU +#define CLOS_MASK_6 0xfffU +#define CLOS_MASK_7 0xfffU +#define CLOS_MASK_8 0xfffU +#define CLOS_MASK_9 0xfffU +#define CLOS_MASK_10 0xfffU +#define CLOS_MASK_11 0xfffU +#define CLOS_MASK_12 0xfffU +#define CLOS_MASK_13 0xfffU +#define CLOS_MASK_14 0xfffU +#define CLOS_MASK_15 0xfffU + +#define VM0_VCPU_CLOS {0U, 0U} +#define VM1_VCPU_CLOS {0U, 0U} +#endif + + +#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \ +noxsave nohpet no_timer_check ignore_loglevel \ +log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi" + +#define VM1_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \ +noxsave nohpet no_timer_check ignore_loglevel \ +log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi" + + +#define VM0_PT_INTX_NUM 0U + +#endif /* MISC_CFG_H */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c b/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c new file mode 100644 index 000000000..eaf709dee --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c b/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c new file mode 100644 index 000000000..021123bb1 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +struct pt_intx_config vm0_pt_intx[1U]; + diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h new file mode 100644 index 000000000..c885dca39 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \ + .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL + +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL + +#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL + +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL + +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL + +#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL + +#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL + +#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL + +#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL + +#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL + +#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL + +#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL + +#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \ + .vbar_base[1] = 0x80000000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL + +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL + +#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL + +#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL + +#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL + +#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \ + .vbar_base[2] = 0x834e7000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \ + .vbar_base[1] = 0x834f6000UL, \ + .vbar_base[5] = 0x834f5000UL + +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL + +#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL + +#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL + +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \ + .vbar_base[2] = 0x834f2000UL + +#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \ + .vbar_base[4] = 0x83200000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c new file mode 100644 index 000000000..bd963ec4d --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include + + +extern struct pt_intx_config vm0_pt_intx[1U]; + +struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { + { /* VM0 */ + CONFIG_PRE_STD_VM(1), + .name = "ACRN PRE-LAUNCHED VM0", + .cpu_affinity = VM0_CONFIG_CPU_AFFINITY, + .guest_flags = 0UL, +#ifdef CONFIG_RDT_ENABLED + .clos = VM0_VCPU_CLOS, +#endif + .memory = { + .start_hpa = VM0_CONFIG_MEM_START_HPA, + .size = VM0_CONFIG_MEM_SIZE, + .start_hpa2 = VM0_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = { + .name = "YOCTO", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = VM0_BOOT_ARGS, + }, + .acpi_config = { + .acpi_mod_tag = "ACPI_VM0", + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 1U, + .t_vuart.vuart_id = 1U, + }, +#ifdef VM0_PASSTHROUGH_TPM + .pt_tpm2 = true, + .mmiodevs[0] = { + .base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA, + .base_hpa = VM0_TPM_BUFFER_BASE_ADDR, + .size = VM0_TPM_BUFFER_SIZE, + }, +#endif +#ifdef P2SB_BAR_ADDR + .pt_p2sb_bar = true, + .mmiodevs[0] = { + .base_gpa = P2SB_BAR_ADDR_GPA, + .base_hpa = P2SB_BAR_ADDR, + .size = P2SB_BAR_SIZE, + }, +#endif + .pt_intx_num = VM0_PT_INTX_NUM, + .pt_intx = &vm0_pt_intx[0U], + }, + { /* VM1 */ + CONFIG_PRE_STD_VM(2), + .name = "ACRN PRE-LAUNCHED VM1", + .cpu_affinity = VM1_CONFIG_CPU_AFFINITY, + .guest_flags = 0UL, +#ifdef CONFIG_RDT_ENABLED + .clos = VM1_VCPU_CLOS, +#endif + .memory = { + .start_hpa = VM1_CONFIG_MEM_START_HPA, + .size = VM1_CONFIG_MEM_SIZE, + .start_hpa2 = VM1_CONFIG_MEM_START_HPA2, + .size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2, + }, + .os_config = { + .name = "YOCTO", + .kernel_type = KERNEL_BZIMAGE, + .kernel_mod_tag = "Linux_bzImage", + .bootargs = VM1_BOOT_ARGS, + }, + .acpi_config = { + .acpi_mod_tag = "ACPI_VM1", + }, + .vuart[0] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM1_BASE, + .irq = COM1_IRQ, + }, + .vuart[1] = { + .type = VUART_LEGACY_PIO, + .addr.port_base = COM2_BASE, + .irq = COM2_IRQ, + .t_vuart.vm_id = 0U, + .t_vuart.vuart_id = 1U, + }, + }, +}; diff --git a/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h new file mode 100644 index 000000000..cff492b90 --- /dev/null +++ b/misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2021 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef VM_CONFIGURATIONS_H +#define VM_CONFIGURATIONS_H + +#include +#include + +/* SOS_VM_NUM can only be 0U or 1U; + * When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; + * MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM; + */ +#define PRE_VM_NUM 2U +#define SOS_VM_NUM 0U +#define MAX_POST_VM_NUM 0U +#define CONFIG_MAX_KATA_VM_NUM 0U + +#define DM_OWNED_GUEST_FLAG_MASK 0UL + +#define VM0_CONFIG_MEM_START_HPA 0x100000000UL +#define VM0_CONFIG_MEM_SIZE 0x20000000UL +#define VM0_CONFIG_MEM_START_HPA2 0x0UL +#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL + +#define VM1_CONFIG_MEM_START_HPA 0x120000000UL +#define VM1_CONFIG_MEM_SIZE 0x20000000UL +#define VM1_CONFIG_MEM_START_HPA2 0x0UL +#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL + +#endif /* VM_CONFIGURATIONS_H */ diff --git a/misc/config_tools/data/generic/hybrid.xml b/misc/config_tools/data/generic_board/hybrid.xml similarity index 99% rename from misc/config_tools/data/generic/hybrid.xml rename to misc/config_tools/data/generic_board/hybrid.xml index 1a8776640..66942a545 100644 --- a/misc/config_tools/data/generic/hybrid.xml +++ b/misc/config_tools/data/generic_board/hybrid.xml @@ -1,5 +1,5 @@ - + n diff --git a/misc/config_tools/data/generic/hybrid_rt.xml b/misc/config_tools/data/generic_board/hybrid_rt.xml similarity index 99% rename from misc/config_tools/data/generic/hybrid_rt.xml rename to misc/config_tools/data/generic_board/hybrid_rt.xml index 38dcde540..428f9ec1d 100644 --- a/misc/config_tools/data/generic/hybrid_rt.xml +++ b/misc/config_tools/data/generic_board/hybrid_rt.xml @@ -1,5 +1,5 @@ - + n diff --git a/misc/config_tools/data/generic/industry.xml b/misc/config_tools/data/generic_board/industry.xml similarity index 99% rename from misc/config_tools/data/generic/industry.xml rename to misc/config_tools/data/generic_board/industry.xml index a29ced9ed..e6b65f843 100644 --- a/misc/config_tools/data/generic/industry.xml +++ b/misc/config_tools/data/generic_board/industry.xml @@ -1,5 +1,5 @@ - + n diff --git a/misc/config_tools/data/generic/industry_launch_2uos.xml b/misc/config_tools/data/generic_board/industry_launch_2uos.xml similarity index 100% rename from misc/config_tools/data/generic/industry_launch_2uos.xml rename to misc/config_tools/data/generic_board/industry_launch_2uos.xml diff --git a/misc/config_tools/data/generic/logical_partition.xml b/misc/config_tools/data/generic_board/logical_partition.xml similarity index 99% rename from misc/config_tools/data/generic/logical_partition.xml rename to misc/config_tools/data/generic_board/logical_partition.xml index 2b8de4076..b67e8a0cb 100644 --- a/misc/config_tools/data/generic/logical_partition.xml +++ b/misc/config_tools/data/generic_board/logical_partition.xml @@ -1,5 +1,5 @@ - + n diff --git a/misc/config_tools/library/hypervisor_license b/misc/config_tools/library/hypervisor_license index 8851f03d8..e9c7d7b5b 100644 --- a/misc/config_tools/library/hypervisor_license +++ b/misc/config_tools/library/hypervisor_license @@ -1,5 +1,5 @@ /* - * Copyright (C) 2020 Intel Corporation. All rights reserved. + * Copyright (C) 2021 Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/misc/config_tools/library/scenario_cfg_lib.py b/misc/config_tools/library/scenario_cfg_lib.py index 29a8d887c..ba470cf1f 100644 --- a/misc/config_tools/library/scenario_cfg_lib.py +++ b/misc/config_tools/library/scenario_cfg_lib.py @@ -1215,8 +1215,8 @@ def check_pt_intx(phys_gsi, virt_gsi): if not phys_gsi and not virt_gsi: return - if not board_cfg_lib.is_matched_board(('ehl-crb-b')): - ERR_LIST["pt_intx"] = "only board ehl-crb-b is supported" + if not board_cfg_lib.is_matched_board(('ehl-crb-b','generic_board')): + ERR_LIST["pt_intx"] = "only board ehl-crb-b/generic_board is supported" return if not VM_DB[common.VM_TYPES[0]]['load_type'] == "PRE_LAUNCHED_VM": diff --git a/misc/config_tools/scenario_config/scenario_cfg_gen.py b/misc/config_tools/scenario_config/scenario_cfg_gen.py index bd822c6a3..a889a7bc4 100755 --- a/misc/config_tools/scenario_config/scenario_cfg_gen.py +++ b/misc/config_tools/scenario_config/scenario_cfg_gen.py @@ -187,7 +187,7 @@ def main(args): else: scen_output = ACRN_CONFIG_DEF + "/" + scenario + "/" - scen_board = scen_output + board_name + "/" + scen_board = scen_output + "/" common.mkdir(scen_board) common.mkdir(scen_output) diff --git a/misc/hv_prebuild/Makefile b/misc/hv_prebuild/Makefile index 3717c835e..846149d94 100644 --- a/misc/hv_prebuild/Makefile +++ b/misc/hv_prebuild/Makefile @@ -18,9 +18,9 @@ ifeq ($(TARGET_DIR),) $(error please specify VM configs directory! ) endif -BOARD_INFO_DIR := $(HV_OBJDIR)/configs/boards/$(BOARD) +BOARD_INFO_DIR := $(HV_OBJDIR)/configs/boards SCENARIO_CFG_DIR := $(HV_OBJDIR)/configs/scenarios/$(SCENARIO) -BOARD_CFG_DIR := $(SCENARIO_CFG_DIR)/$(BOARD) +BOARD_CFG_DIR := $(SCENARIO_CFG_DIR) PRE_BUILD_SRCS += main.c PRE_BUILD_SRCS += static_checks.c