diff --git a/hypervisor/arch/x86/cpu_save_boot_ctx.S b/hypervisor/arch/x86/cpu_save_boot_ctx.S index 612cbd3d3..8fcb60317 100644 --- a/hypervisor/arch/x86/cpu_save_boot_ctx.S +++ b/hypervisor/arch/x86/cpu_save_boot_ctx.S @@ -32,6 +32,13 @@ cpu_primary_save_32: /* Clear Limit field, bit 8-11 */ andl $0x0000f0ff, %ecx mov %ecx, BOOT_CTX_CS_AR_OFFSET(%eax) + + /* Save CS limit field */ + mov %cs, %cx + xor %edx, %edx + lsl %ecx, %edx + mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%eax) + mov %es, BOOT_CTX_ES_SEL_OFFSET(%eax) mov %ss, BOOT_CTX_SS_SEL_OFFSET(%eax) mov %ds, BOOT_CTX_DS_SEL_OFFSET(%eax) @@ -62,6 +69,13 @@ cpu_primary_save_64: /* Clear Limit field, bit 8-11 */ andl $0x0000f0ff, %ecx mov %ecx, BOOT_CTX_CS_AR_OFFSET(%r8) + + /* Save CS limit field */ + mov %cs, %cx + xor %edx, %edx + lsl %ecx, %edx + mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%r8) + mov %es, BOOT_CTX_ES_SEL_OFFSET(%r8) mov %ss, BOOT_CTX_SS_SEL_OFFSET(%r8) mov %ds, BOOT_CTX_DS_SEL_OFFSET(%r8) diff --git a/hypervisor/include/arch/x86/guest/vm0_boot.h b/hypervisor/include/arch/x86/guest/vm0_boot.h index 03b20b38b..176662d3d 100644 --- a/hypervisor/include/arch/x86/guest/vm0_boot.h +++ b/hypervisor/include/arch/x86/guest/vm0_boot.h @@ -22,6 +22,7 @@ #define BOOT_CTX_FS_SEL_OFFSET 276 #define BOOT_CTX_GS_SEL_OFFSET 278 #define BOOT_CTX_CS_AR_OFFSET 248 +#define BOOT_CTX_CS_LIMIT_OFFSET 252 #define BOOT_CTX_EFER_LOW_OFFSET 200 #define BOOT_CTX_EFER_HIGH_OFFSET 204 #define SIZE_OF_BOOT_CTX 296 @@ -40,6 +41,7 @@ #define BOOT_CTX_FS_SEL_OFFSET 276U #define BOOT_CTX_GS_SEL_OFFSET 278U #define BOOT_CTX_CS_AR_OFFSET 248U +#define BOOT_CTX_CS_LIMIT_OFFSET 252U #define BOOT_CTX_EFER_LOW_OFFSET 200U #define BOOT_CTX_EFER_HIGH_OFFSET 204U #define SIZE_OF_BOOT_CTX 296U diff --git a/hypervisor/include/public/acrn_common.h b/hypervisor/include/public/acrn_common.h index 10f288ed3..901c8df37 100644 --- a/hypervisor/include/public/acrn_common.h +++ b/hypervisor/include/public/acrn_common.h @@ -295,7 +295,8 @@ struct acrn_vcpu_regs { uint64_t reserved_64[4]; uint32_t cs_ar; - uint32_t reserved_32[4]; + uint32_t cs_limit; + uint32_t reserved_32[3]; /* don't change the order of following sel */ uint16_t cs_sel;