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hv: vpci: remove pci_msi_cap in pci_pdev

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The MSI Message Address and Message Data have no valid data after Power-ON. So
there's no need to initialize them by reading the data from physical PCI configuration
space.

Tracked-On: #3475
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
This commit is contained in:
Li, Fei1 2019-10-12 17:46:21 +08:00 committed by wenlingz
parent b1e43b4454
commit 0dac373d93
3 changed files with 6 additions and 40 deletions
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26
hypervisor/dm/vpci/vmsi.c
View File

@ -153,21 +153,6 @@ void deinit_vmsi(const struct pci_vdev *vdev)
}
}
/* Read a uint32_t from buffer (little endian) */
static uint32_t buf_read32(const uint8_t buf[])
{
return buf[0] | ((uint32_t)buf[1] << 8U) | ((uint32_t)buf[2] << 16U) | ((uint32_t)buf[3] << 24U);
}
/* Write a uint32_t to buffer (little endian) */
static void buf_write32(uint8_t buf[], uint32_t val)
{
buf[0] = (uint8_t)(val & 0xFFU);
buf[1] = (uint8_t)((val >> 8U) & 0xFFU);
buf[2] = (uint8_t)((val >> 16U) & 0xFFU);
buf[3] = (uint8_t)((val >> 24U) & 0xFFU);
}
/**
* @pre vdev != NULL
* @pre vdev->pdev != NULL
@ -177,18 +162,15 @@ void init_vmsi(struct pci_vdev *vdev)
struct pci_pdev *pdev = vdev->pdev;
uint32_t val;
vdev->msi.capoff = pdev->msi.capoff;
vdev->msi.caplen = pdev->msi.caplen;
vdev->msi.capoff = pdev->msi_capoff;
if (has_msi_cap(vdev)) {
(void)memcpy_s((void *)&vdev->cfgdata.data_8[pdev->msi.capoff], pdev->msi.caplen,
(void *)&pdev->msi.cap[0U], pdev->msi.caplen);
val = pci_pdev_read_cfg(pdev->bdf, vdev->msi.capoff, 4U);
vdev->msi.caplen = ((val & (PCIM_MSICTRL_64BIT << 16U)) != 0U) ? 14U : 10U;
val = buf_read32(&pdev->msi.cap[0U]);
val &= ~((uint32_t)PCIM_MSICTRL_MMC_MASK << 16U);
val &= ~((uint32_t)PCIM_MSICTRL_MME_MASK << 16U);
buf_write32(&vdev->cfgdata.data_8[pdev->msi.capoff], val);
pci_vdev_write_cfg(vdev, vdev->msi.capoff, 4U, val);
}
}

10
hypervisor/hw/pci.c
View File

@ -231,15 +231,7 @@ static void pci_read_cap(struct pci_pdev *pdev)
if ((cap == PCIY_MSI) || (cap == PCIY_MSIX)) {
offset = ptr;
if (cap == PCIY_MSI) {
pdev->msi.capoff = offset;
msgctrl = pci_pdev_read_cfg(pdev->bdf, offset + PCIR_MSI_CTRL, 2U);
len = ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) ? 14U : 10U;
pdev->msi.caplen = len;
/* Copy MSI capability struct into buffer */
for (idx = 0U; idx < len; idx++) {
pdev->msi.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, offset + idx, 1U);
}
pdev->msi_capoff = offset;
} else {
pdev->msix.capoff = offset;
pdev->msix.caplen = MSIX_CAPLEN;

10
hypervisor/include/hw/pci.h
View File

@ -128,7 +128,6 @@
#define PCIM_MSIX_BIR_MASK 0x7U
#define PCIM_MSIX_VCTRL_MASK 0x1U
#define MSI_MAX_CAPLEN 14U
#define MSIX_CAPLEN 12U
#define MSIX_TABLE_ENTRY_SIZE 16U
@ -195,13 +194,6 @@ struct pci_bar {
bool is_64bit_high; /* true if this is the upper 32-bit of a 64-bit bar */
};
/* Basic MSI capability info */
struct pci_msi_cap {
uint32_t capoff;
uint32_t caplen;
uint8_t cap[MSI_MAX_CAPLEN];
};
/* Basic MSIX capability info */
struct pci_msix_cap {
uint32_t capoff;
@ -219,7 +211,7 @@ struct pci_pdev {
/* The bus/device/function triple of the physical PCI device. */
union pci_bdf bdf;
struct pci_msi_cap msi;
uint32_t msi_capoff;
struct pci_msix_cap msix;
};