github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-25 23:13:26 +00:00
Code Issues Projects Releases Wiki Activity

hv: replace CPU_PAGE_SHIFT with PAGE_SHIFT

Browse Source 
- replace CPU_PAGE_SHIFT with PAGE_SHIFT
  These two MACROs are duplicated and PAGE_SHIFT is a more
  reasonable name.
- remove unused MACROs related to page shift in cpu.h

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao 2018-12-03 09:28:37 +08:00 committed by wenlingz
parent 2f15d3569c
commit 0f766ca6b8
5 changed files with 8 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hypervisor/arch/x86/assign.c
View File

@ -91,7 +91,7 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *
bool phys; bool phys;
/* get physical destination cpu mask */ /* get physical destination cpu mask */
dest = (uint32_t)(info->vmsi_addr >> CPU_PAGE_SHIFT) & 0xffU; dest = (uint32_t)(info->vmsi_addr >> PAGE_SHIFT) & 0xffU;
phys = ((info->vmsi_addr & MSI_ADDR_LOG) != MSI_ADDR_LOG); phys = ((info->vmsi_addr & MSI_ADDR_LOG) != MSI_ADDR_LOG);
calcvdest(vm, &vdmask, dest, phys); calcvdest(vm, &vdmask, dest, phys);
@ -112,7 +112,7 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *
/* update physical dest mode & dest field */ /* update physical dest mode & dest field */
info->pmsi_addr = info->vmsi_addr; info->pmsi_addr = info->vmsi_addr;
info->pmsi_addr &= ~0xFF00CU; info->pmsi_addr &= ~0xFF00CU;
info->pmsi_addr |= (dest_mask << CPU_PAGE_SHIFT) | MSI_ADDR_RH | MSI_ADDR_LOG; info->pmsi_addr |= (dest_mask << PAGE_SHIFT) | MSI_ADDR_RH | MSI_ADDR_LOG;
dev_dbg(ACRN_DBG_IRQ, "MSI addr:data = 0x%llx:%x(V) -> 0x%llx:%x(P)", dev_dbg(ACRN_DBG_IRQ, "MSI addr:data = 0x%llx:%x(V) -> 0x%llx:%x(P)",
info->vmsi_addr, info->vmsi_data, info->vmsi_addr, info->vmsi_data,

3
hypervisor/arch/x86/guest/guest.c
View File

@ -664,8 +664,7 @@ uint64_t e820_alloc_low_memory(uint32_t size_arg)
struct e820_entry *entry, *new_entry; struct e820_entry *entry, *new_entry;
/* We want memory in page boundary and integral multiple of pages */ /* We want memory in page boundary and integral multiple of pages */
size = (((size + PAGE_SIZE) - 1U) >> CPU_PAGE_SHIFT) size = (((size + PAGE_SIZE) - 1U) >> PAGE_SHIFT) << PAGE_SHIFT;
<< CPU_PAGE_SHIFT;
for (i = 0U; i < e820_entries; i++) { for (i = 0U; i < e820_entries; i++) {
entry = &e820[i]; entry = &e820[i];

8
hypervisor/arch/x86/vtd.c
View File

@ -871,7 +871,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment, uint8
/* create context table for the bus if not present */ /* create context table for the bus if not present */
context_table_addr = hva2hpa(get_ctx_table(dmar_unit->index, bus)); context_table_addr = hva2hpa(get_ctx_table(dmar_unit->index, bus));
context_table_addr = context_table_addr >> CPU_PAGE_SHIFT; context_table_addr = context_table_addr >> PAGE_SHIFT;
lower = dmar_set_bitslice(lower, lower = dmar_set_bitslice(lower,
ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS, context_table_addr); ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS, context_table_addr);
@ -886,7 +886,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment, uint8
ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS); ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS);
} }
context_table_addr = context_table_addr << CPU_PAGE_SHIFT; context_table_addr = context_table_addr << PAGE_SHIFT;
context_table = (struct dmar_context_entry *)hpa2hva(context_table_addr); context_table = (struct dmar_context_entry *)hpa2hva(context_table_addr);
context_entry = context_table + devfun; context_entry = context_table + devfun;
@ -927,7 +927,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment, uint8
upper = dmar_set_bitslice(upper, upper = dmar_set_bitslice(upper,
CTX_ENTRY_UPPER_DID_MASK, CTX_ENTRY_UPPER_DID_POS, (uint64_t)vmid_to_domainid(domain->vm_id)); CTX_ENTRY_UPPER_DID_MASK, CTX_ENTRY_UPPER_DID_POS, (uint64_t)vmid_to_domainid(domain->vm_id));
lower = dmar_set_bitslice(lower, lower = dmar_set_bitslice(lower,
CTX_ENTRY_LOWER_SLPTPTR_MASK, CTX_ENTRY_LOWER_SLPTPTR_POS, domain->trans_table_ptr >> CPU_PAGE_SHIFT); CTX_ENTRY_LOWER_SLPTPTR_MASK, CTX_ENTRY_LOWER_SLPTPTR_POS, domain->trans_table_ptr >> PAGE_SHIFT);
lower = dmar_set_bitslice(lower, CTX_ENTRY_LOWER_P_MASK, CTX_ENTRY_LOWER_P_POS, 1UL); lower = dmar_set_bitslice(lower, CTX_ENTRY_LOWER_P_MASK, CTX_ENTRY_LOWER_P_POS, 1UL);
context_entry->upper = upper; context_entry->upper = upper;
@ -957,7 +957,7 @@ static int remove_iommu_device(const struct iommu_domain *domain, uint16_t segme
root_entry = root_table + bus; root_entry = root_table + bus;
context_table_addr = dmar_get_bitslice(root_entry->lower, ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS); context_table_addr = dmar_get_bitslice(root_entry->lower, ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS);
context_table_addr = context_table_addr << CPU_PAGE_SHIFT; context_table_addr = context_table_addr << PAGE_SHIFT;
context_table = (struct dmar_context_entry *)hpa2hva(context_table_addr); context_table = (struct dmar_context_entry *)hpa2hva(context_table_addr);
context_entry = context_table + devfun; context_entry = context_table + devfun;

2
hypervisor/debug/shell.c
View File

@ -909,7 +909,7 @@ static void get_entry_info(const struct ptirq_remapping_info *entry, char *type,
if (is_entry_active(entry)) { if (is_entry_active(entry)) {
if (entry->intr_type == PTDEV_INTR_MSI) { if (entry->intr_type == PTDEV_INTR_MSI) {
(void)strcpy_s(type, 16U, "MSI"); (void)strcpy_s(type, 16U, "MSI");
*dest = (entry->msi.pmsi_addr & 0xFF000U) >> CPU_PAGE_SHIFT; *dest = (entry->msi.pmsi_addr & 0xFF000U) >> PAGE_SHIFT;
if ((entry->msi.pmsi_data & APIC_TRIGMOD_LEVEL) != 0U) { if ((entry->msi.pmsi_data & APIC_TRIGMOD_LEVEL) != 0U) {
*lvl_tm = true; *lvl_tm = true;
} else { } else {

4
hypervisor/include/arch/x86/cpu.h
View File

@ -39,12 +39,8 @@
#define CPU_H #define CPU_H
/* Define page size */ /* Define page size */
#define CPU_PAGE_SHIFT 12U
#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL #define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL
#define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT
#define MMU_PDE_PAGE_SHIFT 21U
/* Define CPU stack alignment */ /* Define CPU stack alignment */
#define CPU_STACK_ALIGN 16UL #define CPU_STACK_ALIGN 16UL