diff --git a/hypervisor/Makefile b/hypervisor/Makefile
index decdd7327..e71f4f75a 100644
--- a/hypervisor/Makefile
+++ b/hypervisor/Makefile
@@ -145,6 +145,7 @@ ifeq ($(CONFIG_SHARING_MODE),y)
 C_SRCS += arch/x86/configs/sharing_config.c
 else ifeq ($(CONFIG_PARTITION_MODE),y)
 C_SRCS += arch/x86/configs/partition_config.c
+C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/ve820.c
 endif
 
 C_SRCS += boot/acpi.c
diff --git a/hypervisor/arch/x86/configs/apl-mrb/ve820.c b/hypervisor/arch/x86/configs/apl-mrb/ve820.c
new file mode 100644
index 000000000..296c63080
--- /dev/null
+++ b/hypervisor/arch/x86/configs/apl-mrb/ve820.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2018 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <hypervisor.h>
+#include <e820.h>
+
+const struct e820_entry ve820_entry[NUM_E820_ENTRIES] = {
+	{	/* 0 to mptable */
+		.baseaddr =  0x0U,
+		.length   =  0xEFFFFU,
+		.type     =  E820_TYPE_RAM
+	},
+
+	{	/* mptable 65536U */
+		.baseaddr =  0xF0000U,
+		.length   =  0x10000U,
+		.type     =  E820_TYPE_RESERVED
+	},
+
+	{	/* mptable to lowmem */
+		.baseaddr =  0x100000U,
+		.length   =  0x1FF00000U,
+		.type     =  E820_TYPE_RAM
+	},
+
+	{	/* lowmem to PCI hole */
+		.baseaddr =  0x20000000U,
+		.length   =  0xa0000000U,
+		.type     =  E820_TYPE_RESERVED
+	},
+
+	{	/* PCI hole to 4G */
+		.baseaddr =  0xe0000000U,
+		.length   =  0x20000000U,
+		.type     =  E820_TYPE_RESERVED
+	},
+};
diff --git a/hypervisor/arch/x86/configs/dnv-cb2/ve820.c b/hypervisor/arch/x86/configs/dnv-cb2/ve820.c
new file mode 100644
index 000000000..a18e69dd1
--- /dev/null
+++ b/hypervisor/arch/x86/configs/dnv-cb2/ve820.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2018 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <hypervisor.h>
+#include <e820.h>
+
+const struct e820_entry ve820_entry[NUM_E820_ENTRIES] = {
+	{	/* 0 to mptable */
+		.baseaddr =  0x0U,
+		.length   =  0xEFFFFU,
+		.type     =  E820_TYPE_RAM
+	},
+
+	{	/* mptable 65536U */
+		.baseaddr =  0xF0000U,
+		.length   =  0x10000U,
+		.type     =  E820_TYPE_RESERVED
+	},
+
+	{	/* mptable to lowmem */
+		.baseaddr =  0x100000U,
+		.length   =  0x7FF00000U,
+		.type     =  E820_TYPE_RAM
+	},
+
+	{	/* lowmem to PCI hole */
+		.baseaddr =  0x80000000U,
+		.length   =  0x40000000U,
+		.type     =  E820_TYPE_RESERVED
+	},
+
+	{	/* PCI hole to 4G */
+		.baseaddr =  0xe0000000U,
+		.length   =  0x20000000U,
+		.type     =  E820_TYPE_RESERVED
+	},
+};
diff --git a/hypervisor/arch/x86/e820.c b/hypervisor/arch/x86/e820.c
index e4d29eddb..86390ae28 100644
--- a/hypervisor/arch/x86/e820.c
+++ b/hypervisor/arch/x86/e820.c
@@ -232,9 +232,9 @@ uint32_t create_e820_table(struct e820_entry *param_e820)
 	uint32_t i;
 
 	for (i = 0U; i < NUM_E820_ENTRIES; i++) {
-		param_e820[i].baseaddr = e820_default_entries[i].baseaddr;
-		param_e820[i].length = e820_default_entries[i].length;
-		param_e820[i].type = e820_default_entries[i].type;
+		param_e820[i].baseaddr = ve820_entry[i].baseaddr;
+		param_e820[i].length = ve820_entry[i].length;
+		param_e820[i].type = ve820_entry[i].type;
 	}
 
 	return NUM_E820_ENTRIES;
diff --git a/hypervisor/include/arch/x86/e820.h b/hypervisor/include/arch/x86/e820.h
index 311d8f034..e677d2065 100644
--- a/hypervisor/include/arch/x86/e820.h
+++ b/hypervisor/include/arch/x86/e820.h
@@ -62,7 +62,7 @@ const struct e820_mem_params *get_e820_mem_info(void);
  * there is reserved memory of 64K for MPtable and PCI hole of 512MB
  */
 #define NUM_E820_ENTRIES        5U
-extern const struct e820_entry e820_default_entries[NUM_E820_ENTRIES];
+extern const struct e820_entry ve820_entry[NUM_E820_ENTRIES];
 #endif
 
 #endif
diff --git a/hypervisor/partition/apl-mrb/vm_description.c b/hypervisor/partition/apl-mrb/vm_description.c
index 82b6a6aa0..206fe274b 100644
--- a/hypervisor/partition/apl-mrb/vm_description.c
+++ b/hypervisor/partition/apl-mrb/vm_description.c
@@ -186,35 +186,3 @@ const struct pcpu_vm_config_mapping pcpu_vm_config_map[] = {
 		.is_bsp = true,
 	},
 };
-
-const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
-	{	/* 0 to mptable */
-		.baseaddr =  0x0U,
-		.length   =  0xEFFFFU,
-		.type     =  E820_TYPE_RAM
-	},
-
-	{	/* mptable 65536U */
-		.baseaddr =  0xF0000U,
-		.length   =  0x10000U,
-		.type     =  E820_TYPE_RESERVED
-	},
-
-	{	/* mptable to lowmem */
-		.baseaddr =  0x100000U,
-		.length   =  0x1FF00000U,
-		.type     =  E820_TYPE_RAM
-	},
-
-	{	/* lowmem to PCI hole */
-		.baseaddr =  0x20000000U,
-		.length   =  0xa0000000U,
-		.type     =  E820_TYPE_RESERVED
-	},
-
-	{	/* PCI hole to 4G */
-		.baseaddr =  0xe0000000U,
-		.length   =  0x20000000U,
-		.type     =  E820_TYPE_RESERVED
-	},
-};
diff --git a/hypervisor/partition/dnv-cb2/vm_description.c b/hypervisor/partition/dnv-cb2/vm_description.c
index f6bb32a0c..974267943 100644
--- a/hypervisor/partition/dnv-cb2/vm_description.c
+++ b/hypervisor/partition/dnv-cb2/vm_description.c
@@ -236,35 +236,3 @@ const struct pcpu_vm_config_mapping pcpu_vm_config_map[] = {
 		.is_bsp = true,
 	},
 };
-
-const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
-	{	/* 0 to mptable */
-		.baseaddr =  0x0U,
-		.length   =  0xEFFFFU,
-		.type     =  E820_TYPE_RAM
-	},
-
-	{	/* mptable 65536U */
-		.baseaddr =  0xF0000U,
-		.length   =  0x10000U,
-		.type     =  E820_TYPE_RESERVED
-	},
-
-	{	/* mptable to lowmem */
-		.baseaddr =  0x100000U,
-		.length   =  0x7FF00000U,
-		.type     =  E820_TYPE_RAM
-	},
-
-	{	/* lowmem to PCI hole */
-		.baseaddr =  0x80000000U,
-		.length   =  0x40000000U,
-		.type     =  E820_TYPE_RESERVED
-	},
-
-	{	/* PCI hole to 4G */
-		.baseaddr =  0xe0000000U,
-		.length   =  0x20000000U,
-		.type     =  E820_TYPE_RESERVED
-	},
-};