diff --git a/hypervisor/arch/x86/guest/assign.c b/hypervisor/arch/x86/guest/assign.c
index 609595fb1..37e29a5b9 100644
--- a/hypervisor/arch/x86/guest/assign.c
+++ b/hypervisor/arch/x86/guest/assign.c
@@ -107,13 +107,13 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *
 	dest_mask = calculate_logical_dest_mask(pdmask);
 
 	/* Using phys_irq as index in the corresponding IOMMU */
-	irte.entry.lo_64 = 0UL;
-	irte.entry.hi_64 = 0UL;
-	irte.bits.vector = vector;
-	irte.bits.delivery_mode = delmode;
-	irte.bits.dest_mode = MSI_ADDR_DESTMODE_LOGICAL;
-	irte.bits.rh = MSI_ADDR_RH;
-	irte.bits.dest = dest_mask;
+	irte.value.lo_64 = 0UL;
+	irte.value.hi_64 = 0UL;
+	irte.bits.remap.vector = vector;
+	irte.bits.remap.delivery_mode = delmode;
+	irte.bits.remap.dest_mode = MSI_ADDR_DESTMODE_LOGICAL;
+	irte.bits.remap.rh = MSI_ADDR_RH;
+	irte.bits.remap.dest = dest_mask;
 
 	intr_src.is_msi = true;
 	intr_src.src.msi.value = entry->phys_sid.msi_id.bdf;
@@ -203,13 +203,13 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
 		vector = irq_to_vector(phys_irq);
 		dest_mask = calculate_logical_dest_mask(pdmask);
 
-		irte.entry.lo_64 = 0UL;
-		irte.entry.hi_64 = 0UL;
-		irte.bits.vector = vector;
-		irte.bits.delivery_mode = delmode;
-		irte.bits.dest_mode = IOAPIC_RTE_DESTMODE_LOGICAL;
-		irte.bits.dest = dest_mask;
-		irte.bits.trigger_mode = rte.bits.trigger_mode;
+		irte.value.lo_64 = 0UL;
+		irte.value.hi_64 = 0UL;
+		irte.bits.remap.vector = vector;
+		irte.bits.remap.delivery_mode = delmode;
+		irte.bits.remap.dest_mode = IOAPIC_RTE_DESTMODE_LOGICAL;
+		irte.bits.remap.dest = dest_mask;
+		irte.bits.remap.trigger_mode = rte.bits.trigger_mode;
 
 		intr_src.is_msi = false;
 		intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(phys_irq);
diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c
index aea9fb68f..1d83a6bfe 100644
--- a/hypervisor/arch/x86/vtd.c
+++ b/hypervisor/arch/x86/vtd.c
@@ -1385,7 +1385,7 @@ int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry
 		trigger_mode = 0x0UL;
 	} else {
 		dmar_unit = ioapic_to_dmaru(intr_src->src.ioapic_id, &sid);
-		trigger_mode = irte->bits.trigger_mode;
+		trigger_mode = irte->bits.remap.trigger_mode;
 	}
 
 	if (dmar_unit == NULL) {
@@ -1399,17 +1399,17 @@ int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry
 		ret = -EINVAL;
 	} else {
 		dmar_enable_intr_remapping(dmar_unit);
-		irte->bits.svt = 0x1UL;
-		irte->bits.sq = 0x0UL;
-		irte->bits.sid = sid.value;
-		irte->bits.present = 0x1UL;
-		irte->bits.mode = 0x0UL;
-		irte->bits.trigger_mode = trigger_mode;
-		irte->bits.fpd = 0x0UL;
+		irte->bits.remap.svt = 0x1UL;
+		irte->bits.remap.sq = 0x0UL;
+		irte->bits.remap.sid = sid.value;
+		irte->bits.remap.present = 0x1UL;
+		irte->bits.remap.mode = 0x0UL;
+		irte->bits.remap.trigger_mode = trigger_mode;
+		irte->bits.remap.fpd = 0x0UL;
 		ir_table = (union dmar_ir_entry *)hpa2hva(dmar_unit->ir_table_addr);
 		ir_entry = ir_table + index;
-		ir_entry->entry.hi_64 = irte->entry.hi_64;
-		ir_entry->entry.lo_64 = irte->entry.lo_64;
+		ir_entry->value.hi_64 = irte->value.hi_64;
+		ir_entry->value.lo_64 = irte->value.lo_64;
 
 		iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
 		dmar_invalid_iec(dmar_unit, index, 0U, false);
@@ -1440,7 +1440,7 @@ void dmar_free_irte(const struct intr_source *intr_src, uint16_t index)
 	} else {
 		ir_table = (union dmar_ir_entry *)hpa2hva(dmar_unit->ir_table_addr);
 		ir_entry = ir_table + index;
-		ir_entry->bits.present = 0x0UL;
+		ir_entry->bits.remap.present = 0x0UL;
 
 		iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
 		dmar_invalid_iec(dmar_unit, index, 0U, false);
diff --git a/hypervisor/include/arch/x86/vtd.h b/hypervisor/include/arch/x86/vtd.h
index 45b84c43b..bf18b5339 100644
--- a/hypervisor/include/arch/x86/vtd.h
+++ b/hypervisor/include/arch/x86/vtd.h
@@ -511,24 +511,49 @@ struct dmar_entry {
 };
 
 union dmar_ir_entry {
-	struct dmar_entry entry;
-	struct {
-		uint64_t present:1;
-		uint64_t fpd:1;
-		uint64_t dest_mode:1;
-		uint64_t rh:1;
-		uint64_t trigger_mode:1;
-		uint64_t delivery_mode:3;
-		uint64_t sw_bits:4;
-		uint64_t rsvd_1:3;
-		uint64_t mode:1;
-		uint64_t vector:8;
-		uint64_t rsvd_2:8;
-		uint64_t dest:32;
-		uint64_t sid:16;
-		uint64_t sq:2;
-		uint64_t svt:2;
-		uint64_t rsvd_3:44;
+	struct dmar_entry value;
+
+	union {
+		/* Remapped mode */
+		struct {
+			uint64_t present:1;
+			uint64_t fpd:1;
+			uint64_t dest_mode:1;
+			uint64_t rh:1;
+			uint64_t trigger_mode:1;
+			uint64_t delivery_mode:3;
+			uint64_t avail:4;
+			uint64_t rsvd_1:3;
+			uint64_t mode:1;
+			uint64_t vector:8;
+			uint64_t rsvd_2:8;
+			uint64_t dest:32;
+
+			uint64_t sid:16;
+			uint64_t sq:2;
+			uint64_t svt:2;
+			uint64_t rsvd_3:44;
+		} remap;
+
+		/* Posted mode */
+		struct {
+			uint64_t present:1;
+			uint64_t fpd:1;
+			uint64_t rsvd_1:6;
+			uint64_t avail:4;
+			uint64_t rsvd_2:2;
+			uint64_t urgent:1;
+			uint64_t mode:1;
+			uint64_t vector:8;
+			uint64_t rsvd_3:14;
+			uint64_t pda_l:26;
+
+			uint64_t sid:16;
+			uint64_t sq:2;
+			uint64_t svt:2;
+			uint64_t rsvd_4:12;
+			uint64_t pda_h:32;
+		} post;
 	} bits __packed;
 };