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HV:treewide:Update return type for bit operations fls and clz

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Change the return type of function fls and clz as uint16_t;
When the input is zero, INVALID_BIT_INDEX is returned;
Update temporary variable type and return value check of caller
when it call fls or clz;
When input value is zero, clz returns 32 directly.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER;
        Add type conversion as needed;
        Add "U/UL" for constant value as needed;
        Codeing style fixing.
V2-->V3:
       Use type conversion to remove side effect of
       the variable which stores fls/clz return value;
       fls return INVALID_BIT_INDEX directly when the
       input value is zero.
V3-->v4:
       Clean up comments for fls.

Note: For instruction "bsrl", destination register value
      is undefined when source register value is zero.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Xiangyang Wu
2018-07-02 13:48:11 +08:00
committed by lijinxia
parent 4110f3a87f
commit 13d354e7a6
3 changed files with 41 additions and 23 deletions
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6
hypervisor/lib/div.c
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@@ -16,7 +16,7 @@ static int do_udiv32(uint32_t dividend, uint32_t divisor,
* are valid * clz(dividend)<=clz(divisor)
*/
mask = clz(divisor) - clz(dividend);
mask = (uint32_t)(clz(divisor) - clz(dividend));
/* align divisor and dividend */
divisor <<= mask;
mask = 1U << mask;
@@ -26,8 +26,8 @@ static int do_udiv32(uint32_t dividend, uint32_t divisor,
dividend -= divisor;
res->q.dwords.low |= mask;
}
divisor >>= 1;
} while (((mask >>= 1) != 0) && (dividend != 0));
divisor >>= 1U;
} while (((mask >>= 1U) != 0U) && (dividend != 0U));
/* dividend now contains the reminder */
res->r.dwords.low = dividend;
return 0;