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hv: vPCI: passthrough MSI-X Control Register to guest.

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In spite of Table Size in MSI-X Message Control Register [Bits 10:0] masks as
RO (Register bits are read-only and cannot be altered by software), In Spec
PCIe 6.0, Chap 6.1.4.2 MSI-X Configuration "Depending upon system software
policy, system software, device driver software, or each at different times or
environments may configure a Function’s MSI-X Capability and table structures
with suitable vectors."

This patch just pass through MSI-X Control Register field to guest.

Tracked-On: #7275
Signed-off-by: Fei Li <fei1.li@intel.com>
This commit is contained in:
Fei Li 2022-04-14 17:37:18 +08:00 committed by acrnsi-robot
parent e2f7b1fc51
commit 13e99bc0b9
10 changed files with 58 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/dm/vpci/ivshmem.c
View File

@ -221,7 +221,7 @@ static int32_t ivshmem_mmio_handler(struct io_request *io_req, void *data)
return 0; return 0;
} }
static int32_t read_ivshmem_vdev_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val) static int32_t read_ivshmem_vdev_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
{ {
*val = pci_vdev_read_vcfg(vdev, offset, bytes); *val = pci_vdev_read_vcfg(vdev, offset, bytes);

15
hypervisor/dm/vpci/pci_pt.c
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@ -47,6 +47,21 @@ static inline struct msix_table_entry *get_msix_table_entry(const struct pci_vde
return ((struct msix_table_entry *)hva + index); return ((struct msix_table_entry *)hva + index);
} }
/**
* @brief Reading MSI-X Capability Structure
*
* @pre vdev != NULL
* @pre vdev->pdev != NULL
*/
void read_pt_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
{
if (vdev->msix.is_vmsix_on_msi) {
*val = pci_vdev_read_vcfg(vdev, offset, bytes);
} else {
read_vmsix_cap_reg(vdev, offset, bytes, val);
}
}
/** /**
* @brief Writing MSI-X Capability Structure * @brief Writing MSI-X Capability Structure
* *

2
hypervisor/dm/vpci/vhostbridge.c
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@ -146,7 +146,7 @@ static void deinit_vhostbridge(__unused struct pci_vdev *vdev)
* @pre vdev != NULL * @pre vdev != NULL
* @pre vdev->vpci != NULL * @pre vdev->vpci != NULL
*/ */
static int32_t read_vhostbridge_cfg(const struct pci_vdev *vdev, uint32_t offset, static int32_t read_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val) uint32_t bytes, uint32_t *val)
{ {
*val = pci_vdev_read_vcfg(vdev, offset, bytes); *val = pci_vdev_read_vcfg(vdev, offset, bytes);

6
hypervisor/dm/vpci/vmcs9900.c
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@ -32,12 +32,10 @@ void trigger_vmcs9900_msix(struct pci_vdev *vdev)
} }
} }
static int32_t read_vmcs9900_cfg(const struct pci_vdev *vdev, static int32_t read_vmcs9900_cfg(struct pci_vdev *vdev,
uint32_t offset, uint32_t bytes, uint32_t offset, uint32_t bytes, uint32_t * val)
uint32_t * val)
{ {
*val = pci_vdev_read_vcfg(vdev, offset, bytes); *val = pci_vdev_read_vcfg(vdev, offset, bytes);
return 0; return 0;
} }

28
hypervisor/dm/vpci/vmsix.c
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@ -34,6 +34,34 @@
#include <logmsg.h> #include <logmsg.h>
#include "vpci_priv.h" #include "vpci_priv.h"
/**
* @brief Reading MSI-X Capability Structure
*
* @pre vdev != NULL
* @pre vdev->pdev != NULL
*/
void read_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
{
static const uint8_t msix_pt_mask[12U] = {
0x0U, 0x0U, 0xffU, 0xffU }; /* Only PT MSI-X Message Control Register */
uint32_t virt, phy = 0U, ctrl, pt_mask = 0U;
virt = pci_vdev_read_vcfg(vdev, offset, bytes);
(void)memcpy_s((void *)&pt_mask, bytes, (void *)&msix_pt_mask[offset - vdev->msix.capoff], bytes);
if (pt_mask != 0U) {
phy = pci_pdev_read_cfg(vdev->pdev->bdf, offset, bytes);
ctrl = pci_pdev_read_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
if (((ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U) != vdev->msix.table_count) {
vdev->msix.table_count = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U;
pr_info("%s reprogram MSI-X Table Size to %d\n", __func__, vdev->msix.table_count);
/*In this case, we don't need to unmap msix EPT mapping again. */
ASSERT(vdev->msix.table_count <= (PAGE_SIZE/ MSIX_TABLE_ENTRY_SIZE), "");
}
}
*val = (virt & ~pt_mask) | (phy & pt_mask);
}
/** /**
* @brief Writing MSI-X Capability Structure * @brief Writing MSI-X Capability Structure
* *

6
hypervisor/dm/vpci/vpci.c
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@ -532,15 +532,17 @@ static int32_t write_pt_dev_cfg(struct pci_vdev *vdev, uint32_t offset,
return ret; return ret;
} }
static int32_t read_pt_dev_cfg(const struct pci_vdev *vdev, uint32_t offset, static int32_t read_pt_dev_cfg(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val) uint32_t bytes, uint32_t *val)
{ {
int32_t ret = 0; int32_t ret = 0;
if (cfg_header_access(offset)) { if (cfg_header_access(offset)) {
read_cfg_header(vdev, offset, bytes, val); read_cfg_header(vdev, offset, bytes, val);
} else if (msicap_access(vdev, offset) || msixcap_access(vdev, offset)) { } else if (msicap_access(vdev, offset)) {
*val = pci_vdev_read_vcfg(vdev, offset, bytes); *val = pci_vdev_read_vcfg(vdev, offset, bytes);
} else if (msixcap_access(vdev, offset)) {
read_pt_vmsix_cap_reg(vdev, offset, bytes, val);
} else if (sriovcap_access(vdev, offset)) { } else if (sriovcap_access(vdev, offset)) {
read_sriov_cap_reg(vdev, offset, bytes, val); read_sriov_cap_reg(vdev, offset, bytes, val);
} else { } else {

2
hypervisor/dm/vpci/vpci_bridge.c
View File

@ -80,7 +80,7 @@ static void deinit_vpci_bridge(__unused struct pci_vdev *vdev)
vdev->user = NULL; vdev->user = NULL;
} }
static int32_t read_vpci_bridge_cfg(const struct pci_vdev *vdev, uint32_t offset, static int32_t read_vpci_bridge_cfg(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val) uint32_t bytes, uint32_t *val)
{ {
if ((offset + bytes) <= 0x100U) { if ((offset + bytes) <= 0x100U) {

2
hypervisor/dm/vpci/vpci_priv.h
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@ -153,7 +153,9 @@ void deinit_vmsi(const struct pci_vdev *vdev);
void init_vmsix_pt(struct pci_vdev *vdev); void init_vmsix_pt(struct pci_vdev *vdev);
int32_t add_vmsix_capability(struct pci_vdev *vdev, uint32_t entry_num, uint8_t bar_num); int32_t add_vmsix_capability(struct pci_vdev *vdev, uint32_t entry_num, uint8_t bar_num);
void read_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
bool write_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val); bool write_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
void read_pt_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
void write_pt_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val); void write_pt_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
uint32_t rw_vmsix_table(struct pci_vdev *vdev, struct io_request *io_req); uint32_t rw_vmsix_table(struct pci_vdev *vdev, struct io_request *io_req);
int32_t vmsix_handle_table_mmio_access(struct io_request *io_req, void *priv_data); int32_t vmsix_handle_table_mmio_access(struct io_request *io_req, void *priv_data);

2
hypervisor/dm/vpci/vroot_port.c
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@ -76,7 +76,7 @@ static void deinit_vrp(__unused struct pci_vdev *vdev)
vdev->user = NULL; vdev->user = NULL;
} }
static int32_t read_vrp_cfg(const struct pci_vdev *vdev, uint32_t offset, static int32_t read_vrp_cfg(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val) uint32_t bytes, uint32_t *val)
{ {
*val = pci_vdev_read_vcfg(vdev, offset, bytes); *val = pci_vdev_read_vcfg(vdev, offset, bytes);

2
hypervisor/include/dm/vpci.h
View File

@ -104,7 +104,7 @@ struct pci_vdev_ops {
void (*init_vdev)(struct pci_vdev *vdev); void (*init_vdev)(struct pci_vdev *vdev);
void (*deinit_vdev)(struct pci_vdev *vdev); void (*deinit_vdev)(struct pci_vdev *vdev);
int32_t (*write_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val); int32_t (*write_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
int32_t (*read_vdev_cfg)(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val); int32_t (*read_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
}; };
struct pci_vdev { struct pci_vdev {