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https://github.com/projectacrn/acrn-hypervisor.git
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hv: add SRIOV capability read/write entries
Introduce SRIOV capability field for pci_vdev and add SRIOV capability interception entries. Tracked-On: #4433 Signed-off-by: Yuan Liu <yuan1.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -294,6 +294,7 @@ VP_DM_C_SRCS += dm/vpci/vpci_bridge.c
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VP_DM_C_SRCS += dm/vpci/pci_pt.c
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VP_DM_C_SRCS += dm/vpci/vmsi.c
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VP_DM_C_SRCS += dm/vpci/vmsix.c
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VP_DM_C_SRCS += dm/vpci/vsriov.c
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VP_DM_C_SRCS += arch/x86/guest/vlapic.c
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VP_DM_C_SRCS += arch/x86/guest/pm.c
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VP_DM_C_SRCS += arch/x86/guest/assign.c
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@ -357,6 +357,7 @@ static void vpci_init_pt_dev(struct pci_vdev *vdev)
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*/
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init_vmsi(vdev);
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init_vmsix(vdev);
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init_vsriov(vdev);
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init_vdev_pt(vdev);
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assign_vdev_pt_iommu_domain(vdev);
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@ -381,6 +382,8 @@ static int32_t vpci_write_pt_dev_cfg(struct pci_vdev *vdev, uint32_t offset,
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vmsi_write_cfg(vdev, offset, bytes, val);
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} else if (msixcap_access(vdev, offset)) {
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vmsix_write_cfg(vdev, offset, bytes, val);
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} else if (sriovcap_access(vdev, offset)) {
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write_sriov_cap_reg(vdev, offset, bytes, val);
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} else if (offset == PCIR_COMMAND) {
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vdev_pt_write_command(vdev, (bytes > 2U) ? 2U : bytes, (uint16_t)val);
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} else {
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@ -410,6 +413,8 @@ static int32_t vpci_read_pt_dev_cfg(const struct pci_vdev *vdev, uint32_t offset
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vmsi_read_cfg(vdev, offset, bytes, val);
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} else if (msixcap_access(vdev, offset)) {
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vmsix_read_cfg(vdev, offset, bytes, val);
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} else if (sriovcap_access(vdev, offset)) {
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read_sriov_cap_reg(vdev, offset, bytes, val);
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} else {
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if (is_postlaunched_vm(vdev->vpci->vm) &&
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in_range(offset, PCIR_INTERRUPT_LINE, 4U)) {
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@ -101,6 +101,22 @@ static inline bool msixcap_access(const struct pci_vdev *vdev, uint32_t offset)
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return (has_msix_cap(vdev) && in_range(offset, vdev->msix.capoff, vdev->msix.caplen));
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}
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/*
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* @pre vdev != NULL
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*/
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static inline bool has_sriov_cap(const struct pci_vdev *vdev)
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{
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return (vdev->sriov.capoff != 0U);
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}
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/*
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* @pre vdev != NULL
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*/
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static inline bool sriovcap_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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return (has_sriov_cap(vdev) && in_range(offset, vdev->sriov.capoff, vdev->sriov.caplen));
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}
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/**
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* @pre vdev != NULL
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*/
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@ -140,6 +156,10 @@ void vmsix_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes
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void vmsix_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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void deinit_vmsix(const struct pci_vdev *vdev);
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void init_vsriov(struct pci_vdev *vdev);
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void read_sriov_cap_reg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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void write_sriov_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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uint32_t pci_vdev_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
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void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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64
hypervisor/dm/vpci/vsriov.c
Normal file
64
hypervisor/dm/vpci/vsriov.c
Normal file
@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <ptdev.h>
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#include <vpci.h>
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/**
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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void init_vsriov(struct pci_vdev *vdev)
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{
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struct pci_pdev *pdev = vdev->pdev;
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vdev->sriov.capoff = pdev->sriov.capoff;
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vdev->sriov.caplen = pdev->sriov.caplen;
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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void read_sriov_cap_reg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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/* no need to do emulation, passthrough to physical device directly */
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*val = pci_pdev_read_cfg(vdev->pdev->bdf, offset, bytes);
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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void write_sriov_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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/* Needs to intercept VF_ENABLE and add it in next patch. */
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val);
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}
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@ -69,6 +69,12 @@ struct pci_msix {
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uint32_t table_count;
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};
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/* SRIOV capability structure */
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struct pci_cap_sriov {
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uint32_t capoff;
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uint32_t caplen;
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};
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union pci_cfgdata {
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uint8_t data_8[PCIE_CONFIG_SPACE_SIZE];
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uint16_t data_16[PCIE_CONFIG_SPACE_SIZE >> 1U];
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@ -98,6 +104,7 @@ struct pci_vdev {
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struct pci_msi msi;
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struct pci_msix msix;
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struct pci_cap_sriov sriov;
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/* Pointer to corresponding PCI device's vm_config */
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struct acrn_vm_pci_dev_config *pci_dev_config;
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