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dm: build vRTCT of Software SRAM for Post-launch RTVM

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This patch prepares vRTCT for post-RTVM instead of
  pass-thru native RTCT:
   - Configurations are based on Service VM native RTCT.
   - Remap vLAPIC IDs in vRTCT.
   - Remap base address of SW SRAM memory regions
     from HPA to GPA.
   - HPA base of Software SRAM shall be parsed from PTCT
     instead of hardcoding.

Tracked-On: #5649
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Yonghua Huang
2021-01-26 15:16:25 +08:00
committed by wenlingz
parent 3005d074f0
commit 154a446c5c
8 changed files with 450 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
devicemodel/include/acpi.h
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@@ -39,6 +39,27 @@
#define IO_PMTMR 0x0 /* PM Timer is disabled in ACPI */
struct acpi_table_hdr {
/* ASCII table signature */
char signature[4];
/* Length of table in bytes, including this header */
uint32_t length;
/* ACPI Specification minor version number */
uint8_t revision;
/* To make sum of entire table == 0 */
uint8_t checksum;
/* ASCII OEM identification */
char oem_id[6];
/* ASCII OEM table identification */
char oem_table_id[8];
/* OEM revision number */
uint32_t oem_revision;
/* ASCII ASL compiler vendor ID */
char asl_compiler_id[4];
/* ASL compiler version */
uint32_t asl_compiler_revision;
} __packed;
/* All dynamic table entry no. */
#define NHLT_ENTRY_NO 8

36
devicemodel/include/rtct.h
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@@ -7,10 +7,46 @@
#ifndef RTCT_H
#define RTCT_H
#define RTCT_ENTRY_TYPE_PTCD_LIMIT 1U
#define RTCT_ENTRY_TYPE_PTCM_BINARY 2U
#define RTCT_ENTRY_TYPE_WRC_L3_MASKS 3U
#define RTCT_ENTRY_TYPE_GT_L3_MASKS 4U
#define RTCT_ENTRY_TYPE_PSRAM 5U
#define RTCT_ENTRY_TYPE_STREAM_DATAPATH 6U
#define RTCT_ENTRY_TYPE_TIMEAWARE_SUBSYS 7U
#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
/* TODO: Move to high-memory region. */
#define SOFTWARE_SRAM_BASE_HPA 0x40080000UL
#define SOFTWARE_SRAM_BASE_GPA 0x40080000UL
#define SOFTWARE_SRAM_MAX_SIZE 0x00800000UL
struct rtct_entry {
uint16_t size;
uint16_t format;
uint32_t type;
uint32_t data[64];
} __packed;
struct rtct_entry_data_psram {
uint32_t cache_level;
uint64_t base;
uint32_t ways;
uint32_t size;
uint32_t apic_id_tbl[64];
} __packed;
struct rtct_entry_data_mem_hi_latency {
uint32_t hierarchy;
uint32_t clock_cycles;
uint32_t apic_id_tbl[64];
} __packed;
uint64_t get_software_sram_base_hpa(void);
uint64_t get_software_sram_size(void);
uint8_t *build_vrtct(struct vmctx *ctx, void *cfg);
#endif /* RTCT_H */

8
devicemodel/include/types.h
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@@ -89,6 +89,14 @@ flsl(uint64_t mask)
return mask ? 64 - __builtin_clzl(mask) : 0;
}
/* Returns the number of 1-bits in bits. */
static inline int
bitmap_weight(uint64_t bits)
{
return __builtin_popcountl(bits);
}
/* memory barrier */
#define mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })

1
devicemodel/include/vmmapi.h
View File

@@ -140,6 +140,7 @@ int vm_add_hv_vdev(struct vmctx *ctx, struct acrn_emul_dev *dev);
int vm_remove_hv_vdev(struct vmctx *ctx, struct acrn_emul_dev *dev);
int acrn_parse_cpu_affinity(char *arg);
uint64_t vm_get_cpu_affinity_dm(void);
int vm_create_vcpu(struct vmctx *ctx, uint16_t vcpu_id);
int vm_set_vcpu_regs(struct vmctx *ctx, struct acrn_set_vcpu_regs *cpu_regs);