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doc: add module design for peripheral vhost_bridge device
GAI Tooling Notice: These contents may have been developed with support from one or more generative artificial intelligence solutions. This patch is to add doxygen style comments for some elements in vp-dm_vperipheral vhost_bridge module. Tracked-On: #8665 Signed-off-by: Haiwei Li <haiwei.li@intel.com>
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Haiwei Li
acrnsi-robot
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@ -1,6 +1,6 @@
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/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018-2022 Intel Corporation.
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* Copyright (c) 2018-2024 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -39,51 +39,91 @@
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#include <vacpi.h>
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @addtogroup vp-dm_vperipheral
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*
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* @{
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*/
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/* The chart below shows the hostbridge DID high-byte of the platform later than broadwell, whose PCIEXBAR are always
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located in the PCI hostbridge config space at the offset 0x60. This chart may need further extension in the future
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--------------------------------------------------------------------------------------
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platform | hostbridge DID high-byte
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--------------------------------------------------------------------------------------
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SKL(6-gen) | 0x19
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APL(6-gen Atom) | 0x5a
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KBL(7/8-gen) | 0x59
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CFL/CFL-R(8/9-gen) | 0x3e
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ICL(10-gen) | 0x9b
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EHL(11-gen) | 0x45
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TGL(11-gen) | 0x9a
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--------------------------------------------------------------------------------------
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/**
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* @file
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* @brief Implementation of virtual PCI host bridge.
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*
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* This file defines operations to support virtual PCI host bridge. All the operation related APIs are registered as the
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* callbacks in the global variable "struct pci_vdev_ops vhostbridge_ops".
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*/
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/*
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The chart below shows the hostbridge DID high-byte of the platform later than broadwell, whose PCIEXBAR are always
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located in the PCI hostbridge config space at the offset 0x60. This chart may need further extension in the future
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--------------------------------------------------------------------------------------
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platform | hostbridge DID high-byte
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--------------------------------------------------------------------------------------
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SKL(6-gen) | 0x19
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APL(6-gen Atom) | 0x5a
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KBL(7/8-gen) | 0x59
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CFL/CFL-R(8/9-gen) | 0x3e
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ICL(10-gen) | 0x9b
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EHL(11-gen) | 0x45
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TGL(11-gen) | 0x9a
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--------------------------------------------------------------------------------------
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*/
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static const uint32_t hostbridge_did_highbytes[] = {0x19U, 0x5aU, 0x59U, 0x3eU, 0x9aU, 0x45U, 0x9bU};
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/*
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The vhostbridge we currently emulated is "Celeron N3350/Pentium N4200/Atom E3900 Series Host Bridge",
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which belongs to Intel Appollo Lake processors family, and the device id is 5af0
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TODO:
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1. In the future, we may add one or more virtual hostbridges for CPUs that are incompatible in layout with the current
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one
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2. Besides PCIEXBAR(0x60), there are also some registers needs to be emulated more precisely rather than be treated as
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read-only and hard-coded, listed below:
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TODO:
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1. In the future, we may add one or more virtual hostbridges for CPUs that are incompatible in layout with the current one
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2. Besides PCIEXBAR(0x60), there are also some registers needs to be emulated more precisely rather than be treated as read-only and hard-coded, listed below:
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----------------------------------------------------------------------------------------------------------------
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reg | offset | length | current status | remark
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----------------------------------------------------------------------------------------------------------------
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STATUS_COMMAND | 0x8 | dword | unemulated | pci status and command
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SVID_SID | 0x2C | dword | unemulated | subsys id and subsys vendor id
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MCHBAR | 0x48 | qword | hard-coded | BAR of memory controller hub
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GGC | 0x50 | dword | hard-coded | graphics & mem controller hub graphics CR
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DEVEN | 0x54 | dword | hard-coded | device enable register
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PAVPC | 0x58 | dword | hard-coded | protected audio video path control
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TOUUD | 0xA8 | qword | hard-coded | top of upper usable DRAM
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BDSM | 0xB0 | dword | hard-coded | base of data stolen memory
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BGSM | 0xB4 | dword | hard-coded | base of graphics stolen memory
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TSEGMB | 0xB8 | dword | hard-coded | top segmentmemory base
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TOLUD | 0xBC | dword | hard-coded | top of lower usable dram
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SKPD | 0xDC | dword | unemulated | scratchpad
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CAPID0_CAPCTRL0 | 0xe0 | dword | hard-coded | capability 0 control
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----------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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reg |offset |length |current status |remark
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-----------------------------------------------------------------------------------------------
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STATUS_COMMAND |0x8 |dword |unemulated |pci status and command
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SVID_SID |0x2C |dword |unemulated |subsys id and subsys vendor id
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MCHBAR |0x48 |qword |hard-coded |BAR of memory controller hub
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GGC |0x50 |dword |hard-coded |graphics & mem controller hub graphics CR
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DEVEN |0x54 |dword |hard-coded |device enable register
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PAVPC |0x58 |dword |hard-coded |protected audio video path control
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TOUUD |0xA8 |qword |hard-coded |top of upper usable DRAM
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BDSM |0xB0 |dword |hard-coded |base of data stolen memory
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BGSM |0xB4 |dword |hard-coded |base of graphics stolen memory
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TSEGMB |0xB8 |dword |hard-coded |top segmentmemory base
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TOLUD |0xBC |dword |hard-coded |top of lower usable dram
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SKPD |0xDC |dword |unemulated |scratchpad
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CAPID0_CAPCTRL0 |0xe0 |dword |hard-coded |capability 0 control
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-----------------------------------------------------------------------------------------------
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*/
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/**
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* @brief Initialize the virtual host bridge.
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*
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* A host bridge is a PCI device that is used to support the pci devices under it. This function initializes the
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* specified virtual PCI device as a host bridge. It's usually called during the initialization of a VM.
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*
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* This function emulates the virtual host bridge as a "Celeron N3350/Pentium N4200/Atom E3900 Series Host Bridge",
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* which belongs to Intel Apollo Lake processors family, and the device id is 0x5af0. Per "Section 9 C-Unit in Intel®
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* Pentium® and Celeron® Processor N- and J- Series, Datasheet Volume 2", it initializes related type info registers in
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* configuration space.
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* PCI Express Enhanced Configuration Range Base Address Register (PCIEXBAR) is emulated differently for pre-launched
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* VMs and Service VM, to support PCI Express Enhanced Configuration Access Mechanism (ECAM).
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* - For a pre-launched VM, it is emulated as 'USER_VM_VIRT_PCI_MMCFG_BASE | 0x1'. USER_VM_VIRT_PCI_MMCFG_BASE
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* (0xE0000000) is the hard-coded virtual PCI MMCFG address base for pre/post-launched VMs. Bit 0 is set to 1 to
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* indicate that the base address defined in the PCIEXBAR register is active.
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* - For a Service VM, it is emulated to be the same value as the physical PCIEXBAR. It is not used for now, mainly for
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* feature extension in the future.
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* Finally, it sets the field parent_user to NULL and the field user to vdev, indicating that this vPCI bridge is used
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* by a VM.
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*
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* @param[inout] vdev Pointer to the virtual PCI device to be initialized.
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*
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* @return None
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*
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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*
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* @post N/A
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*/
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static void init_vhostbridge(struct pci_vdev *vdev)
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{
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union pci_bdf hostbridge_bdf = {.value = 0x0U};
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@ -133,11 +173,13 @@ static void init_vhostbridge(struct pci_vdev *vdev)
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*/
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pciexbar_low = USER_VM_VIRT_PCI_MMCFG_BASE | 0x1U;
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} else {
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/* Inject physical ECAM value to Service VM vhostbridge since Service VM may check PCIe-MMIO Base Address with it */
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/* Inject physical ECAM value to Service VM vhostbridge since Service VM may check PCIe-MMIO Base
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Address with it */
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phys_did = pci_pdev_read_cfg(hostbridge_bdf, PCIR_DEVICE, 2);
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for (i = 0U; i < (sizeof(hostbridge_did_highbytes) / sizeof(uint32_t)); i++) {
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if (((phys_did & 0xff00U) >> 8) == hostbridge_did_highbytes[i]) {
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/* The offset of PCIEXBAR register is 0x60 on Intel platforms, and no counter-case is encountered yet */
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/* The offset of PCIEXBAR register is 0x60 on Intel platforms, and no counter-case is
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encountered yet */
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pciexbar_low = pci_pdev_read_cfg(hostbridge_bdf, 0x60U, 4);
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pciexbar_high = pci_pdev_read_cfg(hostbridge_bdf, 0x64U, 4);
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break;
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@ -152,16 +194,48 @@ static void init_vhostbridge(struct pci_vdev *vdev)
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vdev->user = vdev;
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}
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static void deinit_vhostbridge(__unused struct pci_vdev *vdev)
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/**
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* @brief Deinitialize the virtual host bridge.
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*
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* This function deinitializes the specified virtual PCI device that was previously initialized as a host bridge.
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*
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* For the specified vdev, it sets the fields parent_user and user to NULL, indicating that this virtual device is not
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* owned by any VM.
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*
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* @param[inout] vdev Pointer to the virtual PCI device.
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*
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* @return None
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*
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* @pre vdev != NULL
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*
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* @post N/A
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*/
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static void deinit_vhostbridge(struct pci_vdev *vdev)
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{
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vdev->parent_user = NULL;
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vdev->user = NULL;
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}
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/**
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* @brief Read the configuration space of the virtual host bridge.
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*
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* This function reads the configuration space of the specified virtual PCI device that is configured as a host bridge.
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* It is used to retrieve specific configuration data of the virtual host bridge for further processing or validation.
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*
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* It reads the configuration space of the virtual host bridge and stores the read configuration data in the provided
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* buffer.
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*
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* @param[in] vdev Pointer to the virtual PCI device whose configuration space is to be read.
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* @param[in] offset Offset within the configuration space to read from.
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* @param[in] bytes Number of bytes to read from the configuration space.
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* @param[inout] val Pointer to the buffer where the read configuration data will be stored.
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*
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* @return Always return 0.
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*
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @pre val != NULL
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*
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* @post retval == 0
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*/
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static int32_t read_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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@ -170,10 +244,25 @@ static int32_t read_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
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return 0;
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}
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/**
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* @brief Write to the virtual host bridge configuration space.
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*
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* This function writes to the configuration space of the specified virtual PCI device that is configured as a host
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* bridge. It is used to update specific configuration settings based on the provided parameters.
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*
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* For the non-BAR configuration space, it writes the provided value to the configuration space of the virtual host
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* bridge. For the BAR configuration space, it is read-only and the write operation is ignored.
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*
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* @param[inout] vdev Pointer to the virtual PCI device whose configuration space is to be written.
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* @param[in] offset Offset within the configuration space to start writing to.
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* @param[in] bytes Number of bytes to write to the configuration space.
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* @param[in] val Value to be written to the configuration space.
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*
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* @return Always return 0.
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*
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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*
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* @post retval == 0
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*/
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static int32_t write_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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@ -184,9 +273,27 @@ static int32_t write_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
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return 0;
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}
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/**
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* @brief Data structure implementation for virtual host bridge operations.
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*
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* Struct pci_vdev_ops is used to define the operations of virtual PCI device and definition here is used to support
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* virtual host bridge.
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*
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* A pre-launched VM may have some pci devices and a host bridge is needed to support these devices. This struct is used
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* to define the operations of virtual host bridge in this case for now.
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*
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* @consistency N/A
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* @alignment N/A
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*
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* @remark N/A
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*/
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const struct pci_vdev_ops vhostbridge_ops = {
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.init_vdev = init_vhostbridge,
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.deinit_vdev = deinit_vhostbridge,
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.write_vdev_cfg = write_vhostbridge_cfg,
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.read_vdev_cfg = read_vhostbridge_cfg,
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};
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/**
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* @}
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*/
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