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HV: remove vdev ops for sharing mode

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Remove vdev ops for sharing mode, directly call the corresponding functions
instead of calling the ops callbacks (indirectly)

Remove alloc_pci_vdev() and merge its code into init_vdev_for_pdev() to simplify code

Remove @pre for local variables

Change the return value from int32_t to void to comply with misra c and
add ASSERT in the functions (if necessary) to verify the assumptions for debug build:
 vmsi_init
 vmsix_init
 vmsi_deinit
 vmsix_deinit

Add @pre for vmsix_init_helper and make it a void function, use ASSERT to verify
the assumption for debug build.

Add ASSERT in get_sos_vm

Tracked-On: #2534
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
dongshen
2019-03-05 17:47:25 -08:00
committed by wenlingz
parent eb4f46987a
commit 19c5342506
6 changed files with 80 additions and 176 deletions
Download Patch File Download Diff File Expand all files Collapse all files

108
hypervisor/dm/vpci/msix.c
View File

@@ -328,74 +328,71 @@ static int32_t vmsix_table_mmio_access_handler(struct io_request *io_req, void *
return ret;
}
static int32_t vmsix_init_helper(struct pci_vdev *vdev)
/**
* @pre vdev != NULL
* @pre vdev->pdev != NULL
* @pre vdev->pdev->msix.table_bar < (PCI_BAR_COUNT - 1U)
*/
static void vmsix_init_helper(struct pci_vdev *vdev)
{
uint32_t i;
uint64_t addr_hi, addr_lo;
struct pci_msix *msix = &vdev->msix;
struct pci_pdev *pdev = vdev->pdev;
struct pci_bar *bar;
int32_t ret;
ASSERT(vdev->pdev->msix.table_bar < (PCI_BAR_COUNT - 1U), "msix->table_bar out of range");
msix->table_bar = pdev->msix.table_bar;
msix->table_offset = pdev->msix.table_offset;
msix->table_count = pdev->msix.table_count;
if (msix->table_bar < (PCI_BAR_COUNT - 1U)) {
/* Mask all table entries */
for (i = 0U; i < msix->table_count; i++) {
msix->tables[i].vector_control = PCIM_MSIX_VCTRL_MASK;
msix->tables[i].addr = 0U;
msix->tables[i].data = 0U;
}
bar = &pdev->bar[msix->table_bar];
if (bar != NULL) {
vdev->msix.mmio_hpa = bar->base;
vdev->msix.mmio_gpa = sos_vm_hpa2gpa(bar->base);
vdev->msix.mmio_size = bar->size;
}
if (msix->mmio_gpa != 0U) {
/*
* PCI Spec: a BAR may also map other usable address space that is not associated
* with MSI-X structures, but it must not share any naturally aligned 4 KB
* address range with one where either MSI-X structure resides.
* The MSI-X Table and MSI-X PBA are permitted to co-reside within a naturally
* aligned 4 KB address range.
*
* If PBA or others reside in the same BAR with MSI-X Table, devicemodel could
* emulate them and maps these memory range at the 4KB boundary. Here, we should
* make sure only intercept the minimum number of 4K pages needed for MSI-X table.
*/
/* The higher boundary of the 4KB aligned address range for MSI-X table */
addr_hi = msix->mmio_gpa + msix->table_offset + (msix->table_count * MSIX_TABLE_ENTRY_SIZE);
addr_hi = round_page_up(addr_hi);
/* The lower boundary of the 4KB aligned address range for MSI-X table */
addr_lo = round_page_down(msix->mmio_gpa + msix->table_offset);
(void)register_mmio_emulation_handler(vdev->vpci->vm, vmsix_table_mmio_access_handler,
addr_lo, addr_hi, vdev);
}
ret = 0;
} else {
pr_err("%s, MSI-X device (%x) invalid table BIR %d", __func__, vdev->pdev->bdf.value, msix->table_bar);
vdev->msix.capoff = 0U;
ret = -EIO;
/* Mask all table entries */
for (i = 0U; i < msix->table_count; i++) {
msix->tables[i].vector_control = PCIM_MSIX_VCTRL_MASK;
msix->tables[i].addr = 0U;
msix->tables[i].data = 0U;
}
return ret;
bar = &pdev->bar[msix->table_bar];
if (bar != NULL) {
vdev->msix.mmio_hpa = bar->base;
vdev->msix.mmio_gpa = sos_vm_hpa2gpa(bar->base);
vdev->msix.mmio_size = bar->size;
}
if (msix->mmio_gpa != 0U) {
/*
* PCI Spec: a BAR may also map other usable address space that is not associated
* with MSI-X structures, but it must not share any naturally aligned 4 KB
* address range with one where either MSI-X structure resides.
* The MSI-X Table and MSI-X PBA are permitted to co-reside within a naturally
* aligned 4 KB address range.
*
* If PBA or others reside in the same BAR with MSI-X Table, devicemodel could
* emulate them and maps these memory range at the 4KB boundary. Here, we should
* make sure only intercept the minimum number of 4K pages needed for MSI-X table.
*/
/* The higher boundary of the 4KB aligned address range for MSI-X table */
addr_hi = msix->mmio_gpa + msix->table_offset + (msix->table_count * MSIX_TABLE_ENTRY_SIZE);
addr_hi = round_page_up(addr_hi);
/* The lower boundary of the 4KB aligned address range for MSI-X table */
addr_lo = round_page_down(msix->mmio_gpa + msix->table_offset);
(void)register_mmio_emulation_handler(vdev->vpci->vm, vmsix_table_mmio_access_handler,
addr_lo, addr_hi, vdev);
}
}
/**
* @pre vdev != NULL
*/
int32_t vmsix_init(struct pci_vdev *vdev)
void vmsix_init(struct pci_vdev *vdev)
{
struct pci_pdev *pdev = vdev->pdev;
int32_t ret = 0;
vdev->msix.capoff = pdev->msix.capoff;
vdev->msix.caplen = pdev->msix.caplen;
@@ -404,10 +401,8 @@ int32_t vmsix_init(struct pci_vdev *vdev)
(void)memcpy_s((void *)&vdev->cfgdata.data_8[pdev->msix.capoff], pdev->msix.caplen,
(void *)&pdev->msix.cap[0U], pdev->msix.caplen);
ret = vmsix_init_helper(vdev);
vmsix_init_helper(vdev);
}
return ret;
}
/**
@@ -415,20 +410,11 @@ int32_t vmsix_init(struct pci_vdev *vdev)
* @pre vdev->vpci != NULL
* @pre vdev->vpci->vm != NULL
*/
int32_t vmsix_deinit(const struct pci_vdev *vdev)
void vmsix_deinit(const struct pci_vdev *vdev)
{
if (has_msix_cap(vdev)) {
if (vdev->msix.table_count != 0U) {
ptirq_remove_msix_remapping(vdev->vpci->vm, vdev->vbdf.value, vdev->msix.table_count);
}
}
return 0;
}
const struct pci_vdev_ops pci_ops_vdev_msix = {
.init = vmsix_init,
.deinit = vmsix_deinit,
.cfgwrite = vmsix_cfgwrite,
.cfgread = vmsix_cfgread,
};