diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c
index 962b160e2..80d50baee 100644
--- a/hypervisor/arch/x86/cpu.c
+++ b/hypervisor/arch/x86/cpu.c
@@ -193,10 +193,6 @@ void init_pcpu_pre(bool is_bsp)
 		init_intercepted_cat_msr_list();
 #endif
 
-#ifdef CONFIG_RDT_ENABLED
-		init_rdt_info();
-#endif
-
 		/* NOTE: this must call after MMCONFIG is parsed in acpi_fixup() and before APs are INIT.
 		 * We only support platform with MMIO based CFG space access.
 		 * IO port access only support in debug version.
diff --git a/hypervisor/arch/x86/rdt.c b/hypervisor/arch/x86/rdt.c
index d9c4c5625..758837df9 100644
--- a/hypervisor/arch/x86/rdt.c
+++ b/hypervisor/arch/x86/rdt.c
@@ -68,84 +68,6 @@ const struct rdt_info *get_rdt_res_cap_info(int res)
 	return &res_cap_info[res];
 }
 
-/*
- * @pre res == RDT_RESOURCE_L3 || res == RDT_RESOURCE_L2
- */
-static void init_cat_capability(int res)
-{
-	uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
-
-	/* CPUID.(EAX=0x10,ECX=ResID):EAX[4:0] reports the length of CBM supported
-	 * CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] indicates shared cache mask bits
-	 * that are used by other entities such as graphic and H/W outside processor.
-	 * CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
-	 */
-	cpuid_subleaf(CPUID_RDT_ALLOCATION, res_cap_info[res].res_id, &eax, &ebx, &ecx, &edx);
-	res_cap_info[res].res.cache.cbm_len = (uint16_t)((eax & 0x1fU) + 1U);
-	res_cap_info[res].res.cache.bitmask = ebx;
-#ifdef CONFIG_CDP_ENABLED
-	res_cap_info[res].res.cache.is_cdp_enabled = ((ecx & 0x4U) != 0U);
-#else
-	res_cap_info[res].res.cache.is_cdp_enabled = false;
-#endif
-	res_cap_info[res].num_closids = (uint16_t)(edx & 0xffffU) + 1U;
-	if (res_cap_info[res].res.cache.is_cdp_enabled) {
-		res_cap_info[res].num_closids >>= 1U;
-	}
-}
-
-static void init_mba_capability(int res)
-{
-	uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
-
-	/* CPUID.(EAX=0x10,ECX=ResID):EAX[11:0] reports maximum MBA throttling value supported
-	 * CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] reserved
-	 * CPUID.(EAX=10H, ECX=ResID=3):ECX[2] reports if response of the delay values is linear
-	 * CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
-	 */
-	cpuid_subleaf(CPUID_RDT_ALLOCATION, res_cap_info[res].res_id, &eax, &ebx, &ecx, &edx);
-	res_cap_info[res].res.membw.mba_max = (uint16_t)((eax & 0xfffU) + 1U);
-	res_cap_info[res].res.membw.delay_linear = ((ecx & 0x4U) != 0U);
-	res_cap_info[res].num_closids = (uint16_t)(edx & 0xffffU) + 1U;
-}
-
-/*
- * @pre common_num_closids > 0U
- */
-void init_rdt_info(void)
-{
-	uint8_t i;
-	uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
-
-	if (pcpu_has_cap(X86_FEATURE_RDT_A)) {
-		cpuid_subleaf(CPUID_RDT_ALLOCATION, 0U, &eax, &ebx, &ecx, &edx);
-
-		/* If HW supports L3 CAT, EBX[1] is set */
-		if ((ebx & 2U) != 0U) {
-			init_cat_capability(RDT_RESOURCE_L3);
-		}
-
-		/* If HW supports L2 CAT, EBX[2] is set */
-		if ((ebx & 4U) != 0U) {
-			init_cat_capability(RDT_RESOURCE_L2);
-		}
-
-		/* If HW supports MBA, EBX[3] is set */
-		if ((ebx & 8U) != 0U) {
-			init_mba_capability(RDT_RESOURCE_MBA);
-		}
-
-		for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
-			/* If num_closids == 0, the resource is not supported. Set the
-			 * common_num_closids as the minimal num_closids of all support rdt resource.
-			 */
-			if ((res_cap_info[i].num_closids > 0U) && (res_cap_info[i].num_closids < common_num_closids)) {
-				common_num_closids = res_cap_info[i].num_closids;
-			}
-		}
-	}
-}
-
 /*
  * @pre res < RDT_NUM_RESOURCES
  * @pre res_clos_info[i].mba_delay <= res_cap_info[res].res.membw.mba_max
diff --git a/hypervisor/include/arch/x86/asm/rdt.h b/hypervisor/include/arch/x86/asm/rdt.h
index 9ea3e2617..807939089 100644
--- a/hypervisor/include/arch/x86/asm/rdt.h
+++ b/hypervisor/include/arch/x86/asm/rdt.h
@@ -43,7 +43,6 @@ struct rdt_info {
 	struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/
 };
 
-void init_rdt_info(void);
 void setup_clos(uint16_t pcpu_id);
 uint64_t clos2pqr_msr(uint16_t clos);
 bool is_platform_rdt_capable(void);