diff --git a/hypervisor/arch/x86/configs/whl-phx-i7.config b/hypervisor/arch/x86/configs/whl-phx-i7.config new file mode 100644 index 000000000..a2a755291 --- /dev/null +++ b/hypervisor/arch/x86/configs/whl-phx-i7.config @@ -0,0 +1,7 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="whl-phx-i7" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x14000000 +CONFIG_SERIAL_LEGACY=y +CONFIG_SERIAL_PIO_BASE=0x240 diff --git a/hypervisor/arch/x86/configs/whl-phx-i7/board.c b/hypervisor/arch/x86/configs/whl-phx-i7/board.c new file mode 100644 index 000000000..5cd03e75f --- /dev/null +++ b/hypervisor/arch/x86/configs/whl-phx-i7/board.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: American Megatrends Inc. + * Version: WL37R107 + * Release Date: 06/24/2020 + * BIOS Revision: 5.13 + * + * Base Board Information + * Manufacturer: Maxtang + * Product Name: WL37 + * Version: V1.0 + */ + +#include +#include +#include +#include +static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = { + { + .type = DRHD0_DEVSCOPE0_TYPE, + .id = DRHD0_DEVSCOPE0_ID, + .bus = DRHD0_DEVSCOPE0_BUS, + .devfun = DRHD0_DEVSCOPE0_PATH, + }, +}; + +static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = { + { + .type = DRHD1_DEVSCOPE0_TYPE, + .id = DRHD1_DEVSCOPE0_ID, + .bus = DRHD1_DEVSCOPE0_BUS, + .devfun = DRHD1_DEVSCOPE0_PATH, + }, + { + .type = DRHD1_DEVSCOPE1_TYPE, + .id = DRHD1_DEVSCOPE1_ID, + .bus = DRHD1_DEVSCOPE1_BUS, + .devfun = DRHD1_DEVSCOPE1_PATH, + }, +}; + +static struct dmar_drhd drhd_info_array[DRHD_COUNT] = { + { + .dev_cnt = DRHD0_DEV_CNT, + .segment = DRHD0_SEGMENT, + .flags = DRHD0_FLAGS, + .reg_base_addr = DRHD0_REG_BASE, + .ignore = DRHD0_IGNORE, + .devices = drhd0_dev_scope + }, + { + .dev_cnt = DRHD1_DEV_CNT, + .segment = DRHD1_SEGMENT, + .flags = DRHD1_FLAGS, + .reg_base_addr = DRHD1_REG_BASE, + .ignore = DRHD1_IGNORE, + .devices = drhd1_dev_scope + }, +}; + +struct dmar_info plat_dmar_info = { + .drhd_count = DRHD_COUNT, + .drhd_units = drhd_info_array, +}; + +#ifdef CONFIG_RDT_ENABLED +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM]; +#endif + +/* Cx data is not available */ +static const struct cpu_cx_data board_cpu_cx[0]; + +/* Px data is not available */ +static const struct cpu_px_data board_cpu_px[0]; + +const struct cpu_state_table board_cpu_state_tbl = { + "Intel(R) Core(TM) i7-8665U CPU @ 1.90GHz", + {(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px, + (uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx} +}; +const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; diff --git a/hypervisor/arch/x86/configs/whl-phx-i7/misc_cfg.h b/hypervisor/arch/x86/configs/whl-phx-i7/misc_cfg.h new file mode 100644 index 000000000..e8913fcfd --- /dev/null +++ b/hypervisor/arch/x86/configs/whl-phx-i7/misc_cfg.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define MAX_PCPU_NUM 4U +#define MAX_PLATFORM_CLOS_NUM 0U +#define ROOTFS_0 "root=/dev/nvme0n1p3 " +#define ROOTFS_1 "root=/dev/sda3 " + +#define SOS_ROOTFS "root=/dev/sda3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 5U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 5U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "hvlog=2M@0xe00000 " \ + "memmap=0x200000$0xe00000" + +#define MAX_HIDDEN_PDEVS_NUM 0U + +#define HI_MMIO_START ~0UL +#define HI_MMIO_END 0UL + +#endif /* MISC_CFG_H */ diff --git a/hypervisor/arch/x86/configs/whl-phx-i7/pci_devices.h b/hypervisor/arch/x86/configs/whl-phx-i7/pci_devices.h new file mode 100644 index 000000000..58ccda680 --- /dev/null +++ b/hypervisor/arch/x86/configs/whl-phx-i7/pci_devices.h @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: American Megatrends Inc. + * Version: WL37R107 + * Release Date: 06/24/2020 + * BIOS Revision: 5.13 + * + * Base Board Information + * Manufacturer: Maxtang + * Product Name: WL37 + * Version: V1.0 + */ + +#ifndef PCI_DEVICES_H_ +#define PCI_DEVICES_H_ + +#define PTDEV_HI_MMIO_SIZE 0x0UL + +#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x06U}, \ + .vbar_base[0] = 0xa1400000UL + +#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1200000UL, \ + .vbar_base[3] = 0xa1220000UL + +#define ETHERNET_CONTROLLER_2 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1300000UL, \ + .vbar_base[3] = 0xa1320000UL + +#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x02U}, \ + .vbar_base[0] = 0xa143d000UL + +#define COMMUNICATION_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U}, \ + .vbar_base[0] = 0xa1443000UL + +#define COMMUNICATION_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x01U}, \ + .vbar_base[0] = 0xa1444000UL + +#define COMMUNICATION_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1441000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x05U, .d = 0x00U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1100000UL + +#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}, \ + .vbar_base[0] = 0xa1438000UL + +#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x04U} + +#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x06U} + +#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x07U} + +#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U} + +#define PCI_BRIDGE_4 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U} + +#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}, \ + .vbar_base[0] = 0xa1436000UL, \ + .vbar_base[2] = 0xa1446000UL + +#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U}, \ + .vbar_base[0] = 0xa143a000UL + +#define SERIAL_BUS_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x02U}, \ + .vbar_base[0] = 0xa143c000UL + +#define SERIAL_BUS_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1442000UL + +#define SERIAL_BUS_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x03U}, \ + .vbar_base[0] = 0xa1447000UL + +#define SERIAL_BUS_CONTROLLER_4 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x01U}, \ + .vbar_base[0] = 0xa143b000UL + +#define SERIAL_BUS_CONTROLLER_5 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x02U}, \ + .vbar_base[0] = 0xa1445000UL + +#define SERIAL_BUS_CONTROLLER_6 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x03U}, \ + .vbar_base[0] = 0xa143e000UL + +#define SERIAL_BUS_CONTROLLER_7 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x06U}, \ + .vbar_base[0] = 0xa1439000UL + +#define SERIAL_BUS_CONTROLLER_8 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}, \ + .vbar_base[0] = 0xfe010000UL + +#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U} + +#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U} + +#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}, \ + .vbar_base[0] = 0xa1430000UL, \ + .vbar_base[4] = 0xa1000000UL + +#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1434000UL, \ + .vbar_base[1] = 0xa1440000UL, \ + .vbar_base[5] = 0xa143f000UL + +#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, \ + .vbar_base[0] = 0xa0000000UL, \ + .vbar_base[2] = 0x90000000UL + +#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1448000UL + +#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}, \ + .vbar_base[0] = 0xa1420000UL + +#endif /* PCI_DEVICES_H_ */ diff --git a/hypervisor/arch/x86/configs/whl-phx-i7/whl-phx-i7_acpi_info.h b/hypervisor/arch/x86/configs/whl-phx-i7/whl-phx-i7_acpi_info.h new file mode 100644 index 000000000..4f99e191c --- /dev/null +++ b/hypervisor/arch/x86/configs/whl-phx-i7/whl-phx-i7_acpi_info.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING! + */ + +#ifndef PLATFORM_ACPI_INFO_H +#define PLATFORM_ACPI_INFO_H + +/* + * BIOS Information + * Vendor: American Megatrends Inc. + * Version: WL37R107 + * Release Date: 06/24/2020 + * BIOS Revision: 5.13 + * + * Base Board Information + * Manufacturer: Maxtang + * Product Name: WL37 + * Version: V1.0 + */ + +/* pm sstate data */ +#define PM1A_EVT_ADDRESS 0x1800UL +#define PM1A_EVT_ACCESS_SIZE 0x2U +#define PM1A_CNT_ADDRESS 0x1804UL +/* S3 is not supported by BIOS */ + +#define WAKE_VECTOR_32 0x8A94808CUL +#define WAKE_VECTOR_64 0x8A948098UL + +#define RESET_REGISTER_ADDRESS 0xCF9UL +#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO +#define RESET_REGISTER_VALUE 0x6U + +/* DRHD of DMAR */ +#define DRHD_COUNT 2U + +#define DRHD0_DEV_CNT 0x1U +#define DRHD0_SEGMENT 0x0U +#define DRHD0_FLAGS 0x0U +#define DRHD0_REG_BASE 0xFED90000UL +#define DRHD0_IGNORE true +#define DRHD0_DEVSCOPE0_TYPE 0x1U +#define DRHD0_DEVSCOPE0_ID 0x0U +#define DRHD0_DEVSCOPE0_BUS 0x0U +#define DRHD0_DEVSCOPE0_PATH 0x10U + +#define DRHD1_DEV_CNT 0x2U +#define DRHD1_SEGMENT 0x0U +#define DRHD1_FLAGS 0x1U +#define DRHD1_REG_BASE 0xFED91000UL +#define DRHD1_IGNORE false +#define DRHD1_DEVSCOPE0_TYPE 0x3U +#define DRHD1_DEVSCOPE0_ID 0x2U +#define DRHD1_DEVSCOPE0_BUS 0x0U +#define DRHD1_DEVSCOPE0_PATH 0xf7U +#define DRHD1_DEVSCOPE1_TYPE 0x4U +#define DRHD1_DEVSCOPE1_ID 0x0U +#define DRHD1_DEVSCOPE1_BUS 0x0U +#define DRHD1_DEVSCOPE1_PATH 0xf6U + +/* PCI mmcfg base of MCFG */ +#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + +#endif /* PLATFORM_ACPI_INFO_H */