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HV: rename vpci files
Renamed 3 files:
hypervisor/dm/vpci/hostbridge.c => vhostbridge.c}
hypervisor/dm/vpci/{msi.c => vmsi.c}
hypervisor/dm/vpci/{msix.c => vmsix.c}
And change Makefile accordingly
Tracked-On: #2534
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
dongshen
committed by
ACRN System Integration
ACRN System Integration
parent
c6a60dd29c
commit
1a3c9b3255
420
hypervisor/dm/vpci/vmsix.c
Normal file
420
hypervisor/dm/vpci/vmsix.c
Normal file
@@ -0,0 +1,420 @@
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/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <vm.h>
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#include <errno.h>
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#include <ptdev.h>
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#include <assign.h>
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#include <vpci.h>
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#include <io.h>
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#include <ept.h>
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#include <mmu.h>
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#include <logmsg.h>
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#include "pci_priv.h"
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/**
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* @pre vdev != NULL
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*/
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static inline bool has_msix_cap(const struct pci_vdev *vdev)
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{
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return (vdev->msix.capoff != 0U);
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool msixcap_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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bool ret = false;
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if (has_msix_cap(vdev)) {
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ret = in_range(offset, vdev->msix.capoff, vdev->msix.caplen);
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}
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return ret;
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}
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static inline bool msixtable_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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return in_range(offset, vdev->msix.table_offset, vdev->msix.table_count * MSIX_TABLE_ENTRY_SIZE);
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}
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static int32_t vmsix_remap_entry(const struct pci_vdev *vdev, uint32_t index, bool enable)
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{
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struct msix_table_entry *pentry;
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struct ptirq_msi_info info;
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void *hva;
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int32_t ret;
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info.is_msix = 1;
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info.vmsi_addr.full = vdev->msix.tables[index].addr;
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info.vmsi_data.full = (enable) ? vdev->msix.tables[index].data : 0U;
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ret = ptirq_msix_remap(vdev->vpci->vm, vdev->vbdf.value, (uint16_t)index, &info);
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if (ret == 0) {
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/* Write the table entry to the physical structure */
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hva = hpa2hva(vdev->msix.mmio_hpa + vdev->msix.table_offset);
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pentry = (struct msix_table_entry *)hva + index;
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/*
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* PCI 3.0 Spec allows writing to Message Address and Message Upper Address
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* fields with a single QWORD write, but some hardware can accept 32 bits
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* write only
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*/
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stac();
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mmio_write32((uint32_t)(info.pmsi_addr.full), (void *)&(pentry->addr));
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mmio_write32((uint32_t)(info.pmsi_addr.full >> 32U), (void *)((char *)&(pentry->addr) + 4U));
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mmio_write32(info.pmsi_data.full, (void *)&(pentry->data));
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mmio_write32(vdev->msix.tables[index].vector_control, (void *)&(pentry->vector_control));
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clac();
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}
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return ret;
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}
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static inline void enable_disable_msix(const struct pci_vdev *vdev, bool enable)
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{
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uint32_t msgctrl;
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if (enable) {
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msgctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
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} else {
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msgctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
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}
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pci_pdev_write_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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/* Do MSI-X remap for all MSI-X table entries in the target device */
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static int32_t vmsix_remap(const struct pci_vdev *vdev, bool enable)
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{
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uint32_t index;
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int32_t ret = 0;
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/* disable MSI-X during configuration */
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enable_disable_msix(vdev, false);
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for (index = 0U; index < vdev->msix.table_count; index++) {
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ret = vmsix_remap_entry(vdev, index, enable);
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if (ret != 0) {
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break;
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}
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}
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (ret == 0) {
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if (enable) {
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enable_disable_pci_intx(vdev->pdev->bdf, false);
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}
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enable_disable_msix(vdev, enable);
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}
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return ret;
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}
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/* Do MSI-X remap for one MSI-X table entry only */
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static int32_t vmsix_remap_one_entry(const struct pci_vdev *vdev, uint32_t index, bool enable)
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{
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uint32_t msgctrl;
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int32_t ret;
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/* disable MSI-X during configuration */
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enable_disable_msix(vdev, false);
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ret = vmsix_remap_entry(vdev, index, enable);
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if (ret == 0) {
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(vdev->pdev->bdf, false);
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}
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/* Restore MSI-X Enable bit */
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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pci_pdev_write_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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}
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return ret;
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}
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int32_t vmsix_cfgread(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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int32_t ret = -ENODEV;
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/* For PIO access, we emulate Capability Structures only */
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if (msixcap_access(vdev, offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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ret = 0;
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}
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return ret;
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}
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int32_t vmsix_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint32_t msgctrl;
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int32_t ret = -ENODEV;
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/* Writing MSI-X Capability Structure */
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if (msixcap_access(vdev, offset)) {
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Write to vdev */
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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/* Writing Message Control field? */
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if ((offset - vdev->msix.capoff) == PCIR_MSIX_CTRL) {
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if (((msgctrl ^ val) & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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if ((val & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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(void)vmsix_remap(vdev, true);
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} else {
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(void)vmsix_remap(vdev, false);
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}
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}
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if (((msgctrl ^ val) & PCIM_MSIXCTRL_FUNCTION_MASK) != 0U) {
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, 2U, val);
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}
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}
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ret = 0;
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}
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return ret;
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}
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static void vmsix_table_rw(struct pci_vdev *vdev, struct mmio_request *mmio, uint32_t offset)
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{
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struct msix_table_entry *entry;
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uint32_t vector_control, entry_offset, table_offset, index;
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bool message_changed = false;
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bool unmasked;
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/* Find out which entry it's accessing */
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table_offset = offset - vdev->msix.table_offset;
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index = table_offset / MSIX_TABLE_ENTRY_SIZE;
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if (index < vdev->msix.table_count) {
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entry = &vdev->msix.tables[index];
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entry_offset = table_offset % MSIX_TABLE_ENTRY_SIZE;
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if (mmio->direction == REQUEST_READ) {
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(void)memcpy_s(&mmio->value, (size_t)mmio->size,
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(void *)entry + entry_offset, (size_t)mmio->size);
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} else {
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/* Only DWORD and QWORD are permitted */
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if ((mmio->size == 4U) || (mmio->size == 8U)) {
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/* Save for comparison */
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vector_control = entry->vector_control;
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/*
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* Writing different value to Message Data/Addr?
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* PCI Spec: Software is permitted to fill in MSI-X Table entry DWORD fields
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* individually with DWORD writes, or software in certain cases is permitted
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* to fill in appropriate pairs of DWORDs with a single QWORD write
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*/
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if (entry_offset < offsetof(struct msix_table_entry, data)) {
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uint64_t qword_mask = ~0UL;
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if (mmio->size == 4U) {
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qword_mask = (entry_offset == 0U) ?
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0x00000000FFFFFFFFUL : 0xFFFFFFFF00000000UL;
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}
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message_changed = ((entry->addr & qword_mask) != (mmio->value & qword_mask));
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} else {
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if (entry_offset == offsetof(struct msix_table_entry, data)) {
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message_changed = (entry->data != (uint32_t)mmio->value);
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}
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}
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/* Write to pci_vdev */
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(void)memcpy_s((void *)entry + entry_offset, (size_t)mmio->size,
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&mmio->value, (size_t)mmio->size);
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/* If MSI-X hasn't been enabled, do nothing */
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if ((pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U)
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& PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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if ((((entry->vector_control ^ vector_control) & PCIM_MSIX_VCTRL_MASK) != 0U)
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|| message_changed) {
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unmasked = ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0U);
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(void)vmsix_remap_one_entry(vdev, index, unmasked);
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}
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}
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} else {
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pr_err("%s, Only DWORD and QWORD are permitted", __func__);
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}
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}
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} else {
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pr_err("%s, invalid arguments %llx - %llx", __func__, mmio->value, mmio->address);
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}
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}
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/**
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* @pre io_req != NULL
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* @pre handler_private_data != NULL
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*/
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static int32_t vmsix_table_mmio_access_handler(struct io_request *io_req, void *handler_private_data)
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{
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struct mmio_request *mmio = &io_req->reqs.mmio;
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struct pci_vdev *vdev;
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int32_t ret = 0;
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uint64_t offset;
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void *hva;
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vdev = (struct pci_vdev *)handler_private_data;
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offset = mmio->address - vdev->msix.mmio_gpa;
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if (msixtable_access(vdev, (uint32_t)offset)) {
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vmsix_table_rw(vdev, mmio, (uint32_t)offset);
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} else {
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hva = hpa2hva(vdev->msix.mmio_hpa + offset);
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/* Only DWORD and QWORD are permitted */
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if ((mmio->size != 4U) && (mmio->size != 8U)) {
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pr_err("%s, Only DWORD and QWORD are permitted", __func__);
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ret = -EINVAL;
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} else if (hva != NULL) {
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stac();
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/* MSI-X PBA and Capability Table could be in the same range */
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if (mmio->direction == REQUEST_READ) {
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/* mmio->size is either 4U or 8U */
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if (mmio->size == 4U) {
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mmio->value = (uint64_t)mmio_read32((const void *)hva);
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} else {
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mmio->value = mmio_read64((const void *)hva);
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}
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} else {
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/* mmio->size is either 4U or 8U */
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if (mmio->size == 4U) {
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mmio_write32((uint32_t)(mmio->value), (void *)hva);
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} else {
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mmio_write64(mmio->value, (void *)hva);
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}
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}
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clac();
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}
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}
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return ret;
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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* @pre vdev->pdev->msix.table_bar < (PCI_BAR_COUNT - 1U)
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*/
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static void vmsix_init_helper(struct pci_vdev *vdev)
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{
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uint32_t i;
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uint64_t addr_hi, addr_lo;
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struct pci_msix *msix = &vdev->msix;
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struct pci_pdev *pdev = vdev->pdev;
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struct pci_bar *bar;
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ASSERT(vdev->pdev->msix.table_bar < (PCI_BAR_COUNT - 1U), "msix->table_bar out of range");
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msix->table_bar = pdev->msix.table_bar;
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msix->table_offset = pdev->msix.table_offset;
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msix->table_count = pdev->msix.table_count;
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/* Mask all table entries */
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for (i = 0U; i < msix->table_count; i++) {
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msix->tables[i].vector_control = PCIM_MSIX_VCTRL_MASK;
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msix->tables[i].addr = 0U;
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msix->tables[i].data = 0U;
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}
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bar = &pdev->bar[msix->table_bar];
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if (bar != NULL) {
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vdev->msix.mmio_hpa = bar->base;
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vdev->msix.mmio_gpa = sos_vm_hpa2gpa(bar->base);
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vdev->msix.mmio_size = bar->size;
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}
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if (msix->mmio_gpa != 0U) {
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/*
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* PCI Spec: a BAR may also map other usable address space that is not associated
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* with MSI-X structures, but it must not share any naturally aligned 4 KB
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* address range with one where either MSI-X structure resides.
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* The MSI-X Table and MSI-X PBA are permitted to co-reside within a naturally
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* aligned 4 KB address range.
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*
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* If PBA or others reside in the same BAR with MSI-X Table, devicemodel could
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* emulate them and maps these memory range at the 4KB boundary. Here, we should
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* make sure only intercept the minimum number of 4K pages needed for MSI-X table.
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*/
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/* The higher boundary of the 4KB aligned address range for MSI-X table */
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addr_hi = msix->mmio_gpa + msix->table_offset + (msix->table_count * MSIX_TABLE_ENTRY_SIZE);
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addr_hi = round_page_up(addr_hi);
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/* The lower boundary of the 4KB aligned address range for MSI-X table */
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addr_lo = round_page_down(msix->mmio_gpa + msix->table_offset);
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(void)register_mmio_emulation_handler(vdev->vpci->vm, vmsix_table_mmio_access_handler,
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addr_lo, addr_hi, vdev);
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}
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}
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/**
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* @pre vdev != NULL
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*/
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void vmsix_init(struct pci_vdev *vdev)
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{
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struct pci_pdev *pdev = vdev->pdev;
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vdev->msix.capoff = pdev->msix.capoff;
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vdev->msix.caplen = pdev->msix.caplen;
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if (has_msix_cap(vdev)) {
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(void)memcpy_s((void *)&vdev->cfgdata.data_8[pdev->msix.capoff], pdev->msix.caplen,
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(void *)&pdev->msix.cap[0U], pdev->msix.caplen);
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vmsix_init_helper(vdev);
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}
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @pre vdev->vpci->vm != NULL
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*/
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void vmsix_deinit(const struct pci_vdev *vdev)
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{
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if (has_msix_cap(vdev)) {
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if (vdev->msix.table_count != 0U) {
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ptirq_remove_msix_remapping(vdev->vpci->vm, vdev->vbdf.value, vdev->msix.table_count);
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}
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}
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}
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