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dm:refine graphics data stolen memory passthru for EHL platform

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EHL graphics data stolen memory(DSM) info has diff with KBL/WHL,
which includes two parts:
(1) DSM register location in pci config: on KBL/WHL, the register
locates on 0X5C, while on EHL, the register locates on 0xC0.
(2) DSM address length: On KBL/WHL,
DSM addr has 32 bits, while on EHL,DSM addr has 64 bits.

Here, refine graphics data stolen memory passthru to enable GVT-d on EHL platforms.

v3 -> v4:
        * add MICRO INTEL_ELKHARTLAKE
v2 -> v3:
	* refine discription,MICRO name
	* refine code style
v1 -> v2:
	* add callback functions for scalability

Tracked-On: projectacrn#4700

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Junming Liu
2020-04-24 19:20:21 +08:00
committed by wenlingz
parent 795225d55e
commit 1da7e4145f
2 changed files with 52 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
devicemodel/include/pcireg.h
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@@ -1066,7 +1066,10 @@
#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */
/* Graphics definitions */
#define INTEL_ELKHARTLAKE 0x4551
#define PCIR_BDSM 0x5C /* BDSM graphics base data of stolen memory register */
#define PCIR_GEN11_BDSM_DW0 0xC0
#define PCIR_GEN11_BDSM_DW1 0xC4
#define PCIM_BDSM_MASK 0xFFF00000
#define PCIR_ASLS_CTL 0xFC /* Opregion start addr register */
#define PCIM_ASLS_OPREGION_MASK 0xFFFFF000 /* opregion need 4KB aligned */