doc: fix misspellings

Fix misspellings missed during regular reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>

doc/developer-guides/hld/hld-hypervisor.rst

@@ -23,4 +23,4 @@ Hypervisor high-level design
    Console, Shell, and vUART <hv-console>
    Hypercall / VHM upcall <hv-hypercall>
    Compile-time configuration <hv-config>
-   RDT support <hv-rdt>
+   RDT support <hv-rdt>

doc/developer-guides/hld/hld-overview.rst

@@ -5,7 +5,7 @@ ACRN high-level design overview
 
 ACRN is an open source reference hypervisor (HV) that runs on top of Intel
 platforms (APL, KBL, etc) for heterogeneous scenarios such as the Software Defined
-Cockpit (SDC), or the In-Vehicle Experience (IVE) for automotives, or HMI & Real-Time OS for industry. ACRN provides embedded hypervisor vendors with a reference
+Cockpit (SDC), or the In-Vehicle Experience (IVE) for automotive, or HMI & Real-Time OS for industry. ACRN provides embedded hypervisor vendors with a reference
 I/O mediation solution with a permissive license and provides auto makers and
 industry users a reference software stack for corresponding use.
 

doc/developer-guides/hld/hld-power-management.rst

@@ -137,7 +137,7 @@ will be dispatched to Device Model and Device Model will emulate the User VM
 power state (pause User VM for S3 and power off User VM for S5)
 
 The VM Manager monitors all User VMs. If all active User VMs are in required
-power state, VM Manager will notify lifecyle manager of Service VM to start
+power state, VM Manager will notify lifecycle manager of Service VM to start
 Service VM power state transition. lifecycle manager of Service VM follows
 a very similar process as User VM for power state transition. The difference
 is Service VM ACPI register writing is trapped to ACRN HV. And ACRN HV will
@@ -163,10 +163,10 @@ For system power state entry:
 1. Service VM received S5 request.
 2. Lifecycle manager in Service VM notify User VM1 and RTVM through
    vUART for S5 request.
-3. Guest lifecycle manager initliaze S5 action. And guest enter S5.
+3. Guest lifecycle manager initialize S5 action. And guest enter S5.
 4. RTOS cleanup rt task, send response of S5 request back to Service
    VM and RTVM enter S5.
-5. After get response from RTVM and all User VM are shutdown, Sevice VM
+5. After get response from RTVM and all User VM are shutdown, Service VM
    enter S5.
 6. OSPM in ACRN hypervisor check all guest in S5 state and shutdown
    whole system.

doc/developer-guides/hld/hld-security.rst

@@ -228,7 +228,7 @@ UEFI Secure Boot implementations use these keys:
 #. Platform Key (PK) is the top-level key in Secure Boot; UEFI supports a single PK,
    which is generally provided by the manufacturer.
 #. Key Exchange Key (KEK) is used to sign Signature and Forbidden Signature Database updates.
-#. Signature Database (db) contains kyes and/or hashes of allowed EFI binaries.
+#. Signature Database (db) contains keys and/or hashes of allowed EFI binaries.
 
 And keys and certificates are in multiple format:
 

doc/developer-guides/hld/hostbridge-virt-hld.rst

@@ -6,7 +6,7 @@ Hostbridge emulation
 Overview
 ********
 
-Hostbridge emulation is based on PCI emulation; however, the hostbridge emulation only sets the PCI configuration space. The device model sets the PCI configuration space for hostbridge in the Service VM ans then exposes it to the User VM to detect the PCI hostbridge.
+Hostbridge emulation is based on PCI emulation; however, the hostbridge emulation only sets the PCI configuration space. The device model sets the PCI configuration space for hostbridge in the Service VM and then exposes it to the User VM to detect the PCI hostbridge.
 
 PCI Host Bridge and hierarchy
 *****************************

doc/developer-guides/hld/hv-memmgt.rst

@@ -96,7 +96,7 @@ After the application processor (AP) receives the IPI CPU startup
 interrupt, it uses the MMU page tables created by the BSP. In order to bring
 the memory access rights into effect, some other APIs are provided:
 enable_paging will enable IA32_EFER.NXE and CR0.WP, enable_smep will
-enable CR4.SMEP, and enable_smap will enale CR4.SMAP.
+enable CR4.SMEP, and enable_smap will enable CR4.SMAP.
 :numref:`hv-mem-init`  describes the hypervisor memory initialization for the BSP
 and APs.
 
@@ -380,7 +380,7 @@ VM Exit about EPT
 
 There are two VM exit handlers for EPT violation and EPT
 misconfiguration in the hypervisor. EPT page tables are
-always configured correctly for the Service ans User VMs. If an EPT misconfiguration is
+always configured correctly for the Service and User VMs. If an EPT misconfiguration is
 detected, a fatal error is reported by the HV. The hypervisor
 uses EPT violation to intercept MMIO access to do device emulation. EPT
 violation handling data flow is described in the

doc/developer-guides/hld/hv-rdt.rst

@@ -199,7 +199,7 @@ sets up CLOS for VMs and the hypervisor itself per the "vm configuration"(:ref:`
 
 - The RDT capabilities are enumerated on the bootstrap processor (BSP) during
   the pCPU pre-initialize stage. The global data structure ``res_cap_info``
-  stores the capabilites of the supported resources.
+  stores the capabilities of the supported resources.
 
 - If CAT or/and MBA is supported, then setup masks array on all APs at the
   pCPU post-initialize stage. The mask values are written to

doc/developer-guides/hld/hv-startup.rst

@@ -139,7 +139,7 @@ The main steps include:
    VM ID is picked, EPT is initialized, e820 table for this VM is prepared,
    I/O bitmap is set up, virtual PIC/IOAPIC/PCI/UART is initialized, EPC for
    virtual SGX is prepared, guest PM IO is set up, IOMMU for PT dev support
-   is enabled, virtual CPUID entries are filled, and vCPUs configred in this VM's
+   is enabled, virtual CPUID entries are filled, and vCPUs configured in this VM's
    ``vm config`` are prepared. For post-launched User VM, the EPT page table and
    e820 table is actually prepared by DM instead of hypervisor.
 
@@ -214,7 +214,7 @@ SW configuration for post-launched User VMs (OVMF SW load as example):
    F-Segment. Refer to :ref:`hld-io-emulation` for details.
 
 -  **E820**: the virtual E820 table is built by the DM then passed to
-   the virtual bootloader. Refer to :ref:`hld-io-emulation` for detais.
+   the virtual bootloader. Refer to :ref:`hld-io-emulation` for details.
 
 -  **Entry address**: the DM will copy User OS kernel(OVMF) image to
    OVMF_NVSTORAGE_OFFSET - normally is @(4G - 2M), and set the entry

doc/developer-guides/hld/hv-virt-interrupt.rst

@@ -20,7 +20,7 @@ the mapping between physical and virtual interrupts for pass-through
 devices. However, a hard RT VM with LAPIC pass-through does own the physical
 maskable external interrupts. On its physical CPUs, interrupts are disabled
 in VMX root mode, while in VMX non-root mode, physical interrupts will be
-deliverd to RT VM directly.
+delivered to RT VM directly.
 
 Emulation for devices is inside the Service VM user space device model, i.e.,
 acrn-dm. However, for performance consideration, vLAPIC, vIOAPIC, and vPIC
@@ -72,7 +72,7 @@ target VCPU.
 Virtual LAPIC
 *************
 
-LAPIC is virtualized for all Guest types: Serice and User VMs. Given support
+LAPIC is virtualized for all Guest types: Service and User VMs. Given support
 by the physical processor, APICv Virtual Interrupt Delivery (VID) is enabled
 and will support Posted-Interrupt feature. Otherwise, it will fall back to
 the legacy virtual interrupt injection mode.
@@ -248,10 +248,10 @@ devices.
    VM via vLAPIC/vIOAPIC. See :ref:`device-assignment`.
 
 -  **For User VM assigned devices**: only PCI devices could be assigned to
-   Uer VM. For the standard VM and soft RT VM, the virtual interrupt
-   injection follows the same way as Servic VM. A virtual interrupt injection
+   User VM. For the standard VM and soft RT VM, the virtual interrupt
+   injection follows the same way as Service VM. A virtual interrupt injection
    operation is triggered when a device's physical interrupt occurs. For the
-   hard RT VM, the physical interrupts are delieverd to VM directly without
+   hard RT VM, the physical interrupts are delivered to VM directly without
    causing VM-exit.
 
 -  **For User VM emulated devices**: DM is responsible for the

doc/developer-guides/hld/hv-vm-management.rst

@@ -14,7 +14,7 @@ VM structure
 The ``acrn_vm`` structure is defined to manage a VM instance, this structure
 maintained a VM's HW resources like vcpu, vpic, vioapic, vuart, vpci. And at
 the same time ``acrn_vm`` structure also recorded a bunch of SW information
-related with corresponding VM, like info for VM indentifier, info for SW
+related with corresponding VM, like info for VM identifier, info for SW
 loader, info for memory e820 entries, info for IO/MMIO handlers, info for
 platform level cpuid entries, and so on.
 

doc/developer-guides/hld/hv-vt-d.rst

@@ -290,7 +290,7 @@ Power Management support for S3
 *******************************
 
 During platform S3 suspend and resume, the VT-d register values are
-lost. ACRN VT-d provides APIs tthat are called during S3 suspend and resume.
+lost. ACRN VT-d provides APIs that are called during S3 suspend and resume.
 
 During S3 suspend, some register values are saved in the memory, and
 DMAR translation is disabled. During S3 resume, the register values