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https://github.com/projectacrn/acrn-hypervisor.git
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dm: virtio-gpu: VGA compability support
Legacy VGA & VBE interface as a common interface is supported by many legacy and modern OS. Many installer of OS distribution use this interface to display the GUI of installer when setup a refresh new installation on bare-metal. Besides, Windows OS always use this interface to display it's BSOD, recovery mode & safe mode GUI. It is need because Windows don't include virtio-gpu driver as their in-box driver, VGA interface will be used before the virtio-gpu driver been installed. To be compatiable with the PCI bar layout of legacy VGA, the layout is refined to meet with the requirement of legacy VGA and modern virtio-gpu. BAR0: VGA Framebuffer memory, 16 MB in size. BAR2: MMIO Space [0x0000~0x03ff] EDID data blob [0x0400~0x041f] VGA ioports registers [0x0500~0x0516] bochs display interface registers [0x1000~0x17ff] Virtio common configuration registers [0x1800~0x1fff] Virtio ISR state registers [0x2000~0x2fff] Virtio device configuration registers [0x3000~0x3fff] Virtio notification registers BAR4: MSI/MSI-X BAR5: Virtio port io Tracked-On: #7210 Signed-off-by: Sun Peng <peng.p.sun@linux.intel.com> Reviewed-by: Zhao, yakui <yakui.zhao@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Sun, Peng
acrnsi-robot
@@ -31,8 +31,6 @@
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#include "types.h"
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struct gfx_ctx;
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struct gfx_ctx_image {
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int vgamode;
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int width;
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@@ -40,6 +38,15 @@ struct gfx_ctx_image {
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uint32_t *data;
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};
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struct gfx_ctx {
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struct gfx_ctx_image *gc_image;
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int raw;
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};
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struct gfx_ctx_image *gc_get_image(struct gfx_ctx *gc);
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struct gfx_ctx *gc_init(int width, int height, void *fbaddr);
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void gc_deinit(struct gfx_ctx *gc);
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void gc_set_fbaddr(struct gfx_ctx *gc, void *fbaddr);
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void gc_resize(struct gfx_ctx *gc, int width, int height);
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#endif /* _GC_H_ */
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199
devicemodel/include/vga.h
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199
devicemodel/include/vga.h
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@@ -0,0 +1,199 @@
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/*
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* Copyright (C) 2022 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*/
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#ifndef _VGA_H_
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#define _VGA_H_
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#include "gc.h"
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#include "vdisplay.h"
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#define VGA_IOPORT_START 0x3c0
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#define VGA_IOPORT_END 0x3df
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/* General registers */
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#define GEN_INPUT_STS0_PORT 0x3c2
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#define GEN_FEATURE_CTRL_PORT 0x3ca
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#define GEN_MISC_OUTPUT_PORT 0x3cc
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#define GEN_INPUT_STS1_MONO_PORT 0x3ba
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#define GEN_INPUT_STS1_COLOR_PORT 0x3da
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#define GEN_IS1_VR 0x08 /* Vertical retrace */
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#define GEN_IS1_DE 0x01 /* Display enable not */
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/* Attribute controller registers. */
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#define ATC_IDX_PORT 0x3c0
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#define ATC_DATA_PORT 0x3c1
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#define ATC_IDX_MASK 0x1f
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#define ATC_PALETTE0 0
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#define ATC_PALETTE15 15
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#define ATC_MODE_CONTROL 16
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#define ATC_MC_IPS 0x80 /* Internal palette size */
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#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */
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#define ATC_OVERSCAN_COLOR 17
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#define ATC_COLOR_PLANE_ENABLE 18
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#define ATC_HORIZ_PIXEL_PANNING 19
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#define ATC_COLOR_SELECT 20
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#define ATC_CS_C67 0x0c /* Color select bits 6+7 */
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#define ATC_CS_C45 0x03 /* Color select bits 4+5 */
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/* Sequencer registers. */
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#define SEQ_IDX_PORT 0x3c4
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#define SEQ_DATA_PORT 0x3c5
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#define SEQ_RESET 0
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#define SEQ_RESET_ASYNC 0x1
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#define SEQ_RESET_SYNC 0x2
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#define SEQ_CLOCKING_MODE 1
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#define SEQ_CM_SO 0x20 /* Screen off */
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#define SEQ_CM_89 0x01 /* 8/9 dot clock */
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#define SEQ_MAP_MASK 2
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#define SEQ_CHAR_MAP_SELECT 3
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#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */
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#define SEQ_CMS_SAH_SHIFT 5
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#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */
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#define SEQ_CMS_SA_SHIFT 2
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#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */
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#define SEQ_CMS_SBH_SHIFT 4
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#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */
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#define SEQ_CMS_SB_SHIFT 0
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#define SEQ_MEMORY_MODE 4
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#define SEQ_MM_C4 0x08 /* Chain 4 */
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#define SEQ_MM_OE 0x04 /* Odd/even */
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#define SEQ_MM_EM 0x02 /* Extended memory */
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/* Graphics controller registers. */
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#define GC_IDX_PORT 0x3ce
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#define GC_DATA_PORT 0x3cf
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#define GC_SET_RESET 0
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#define GC_ENABLE_SET_RESET 1
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#define GC_COLOR_COMPARE 2
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#define GC_DATA_ROTATE 3
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#define GC_READ_MAP_SELECT 4
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#define GC_MODE 5
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#define GC_MODE_OE 0x10 /* Odd/even */
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#define GC_MODE_C4 0x04 /* Chain 4 */
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#define GC_MISCELLANEOUS 6
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#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */
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#define GC_MISC_MM 0x0c /* memory map */
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#define GC_MISC_MM_SHIFT 2
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#define GC_COLOR_DONT_CARE 7
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#define GC_BIT_MASK 8
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/* CRT controller registers. */
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#define CRTC_IDX_MONO_PORT 0x3b4
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#define CRTC_DATA_MONO_PORT 0x3b5
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#define CRTC_IDX_COLOR_PORT 0x3d4
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#define CRTC_DATA_COLOR_PORT 0x3d5
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#define CRTC_HORIZ_TOTAL 0
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#define CRTC_HORIZ_DISP_END 1
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#define CRTC_START_HORIZ_BLANK 2
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#define CRTC_END_HORIZ_BLANK 3
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#define CRTC_START_HORIZ_RETRACE 4
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#define CRTC_END_HORIZ_RETRACE 5
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#define CRTC_VERT_TOTAL 6
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#define CRTC_OVERFLOW 7
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#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
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#define CRTC_OF_VRS9_SHIFT 7
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#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */
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#define CRTC_OF_VDE9_SHIFT 6
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#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
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#define CRTC_OF_VRS8_SHIFT 2
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#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */
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#define CRTC_OF_VDE8_SHIFT 1
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#define CRTC_PRESET_ROW_SCAN 8
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#define CRTC_MAX_SCAN_LINE 9
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#define CRTC_MSL_MSL 0x1f
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#define CRTC_CURSOR_START 10
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#define CRTC_CS_CO 0x20 /* Cursor off */
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#define CRTC_CS_CS 0x1f /* Cursor start */
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#define CRTC_CURSOR_END 11
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#define CRTC_CE_CE 0x1f /* Cursor end */
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#define CRTC_START_ADDR_HIGH 12
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#define CRTC_START_ADDR_LOW 13
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#define CRTC_CURSOR_LOC_HIGH 14
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#define CRTC_CURSOR_LOC_LOW 15
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#define CRTC_VERT_RETRACE_START 16
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#define CRTC_VERT_RETRACE_END 17
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#define CRTC_VRE_MASK 0xf
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#define CRTC_VERT_DISP_END 18
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#define CRTC_OFFSET 19
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#define CRTC_UNDERLINE_LOC 20
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#define CRTC_START_VERT_BLANK 21
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#define CRTC_END_VERT_BLANK 22
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#define CRTC_MODE_CONTROL 23
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#define CRTC_MC_TE 0x80 /* Timing enable */
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#define CRTC_LINE_COMPARE 24
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/* DAC registers */
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#define DAC_MASK 0x3c6
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#define DAC_IDX_RD_PORT 0x3c7
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#define DAC_IDX_WR_PORT 0x3c8
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#define DAC_DATA_PORT 0x3c9
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#define VBE_DISPI_INDEX_ID 0x0
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#define VBE_DISPI_INDEX_XRES 0x1
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#define VBE_DISPI_INDEX_YRES 0x2
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#define VBE_DISPI_INDEX_BPP 0x3
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#define VBE_DISPI_INDEX_ENABLE 0x4
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#define VBE_DISPI_INDEX_BANK 0x5
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#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
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#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
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#define VBE_DISPI_INDEX_X_OFFSET 0x8
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#define VBE_DISPI_INDEX_Y_OFFSET 0x9
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#define VBE_DISPI_INDEX_VIDEO_MEM_64K 0xa
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#define VBE_DISPI_DISABLED 0x00
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#define VBE_DISPI_ENABLED 0x01
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#define VBE_DISPI_GETCAPS 0x02
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#define VBE_DISPI_8BIT_DAC 0x20
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#define VBE_DISPI_LFB_ENABLED 0x40
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#define VBE_DISPI_NOCLEARMEM 0x80
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#define VBE_DISPI_ID0 0xB0C0
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#define VBE_DISPI_ID1 0xB0C1
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#define VBE_DISPI_ID2 0xB0C2
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#define VBE_DISPI_ID3 0xB0C3
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#define VBE_DISPI_ID4 0xB0C4
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#define VBE_DISPI_ID5 0xB0C5
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struct vga {
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bool enable;
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void *dev;
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struct gfx_ctx *gc;
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struct surface surf;
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pthread_t tid;
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struct {
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uint16_t id;
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uint16_t xres;
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uint16_t yres;
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uint16_t bpp;
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uint16_t enable;
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uint16_t bank;
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uint16_t virt_width;
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uint16_t virt_height;
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uint16_t x_offset;
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uint16_t y_offset;
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uint16_t video_memory_64k;
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} __attribute__((packed)) vberegs;
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};
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void *vga_init(struct gfx_ctx *gc, int io_only);
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void vga_render(struct gfx_ctx *gc, void *arg);
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int vga_port_in_handler(struct vmctx *ctx, int in, int port, int bytes,
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uint8_t *val, void *arg);
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int vga_port_out_handler(struct vmctx *ctx, int in, int port, int bytes,
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uint8_t val, void *arg);
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void vga_ioport_write(struct vmctx *ctx, int vcpu, struct vga *vga,
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uint64_t offset, int size, uint64_t value);
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uint64_t vga_ioport_read(struct vmctx *ctx, int vcpu, struct vga *vga,
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uint64_t offset, int size);
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void vga_vbe_write(struct vmctx *ctx, int vcpu, struct vga *vga,
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uint64_t offset, int size, uint64_t value);
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uint64_t vga_vbe_read(struct vmctx *ctx, int vcpu, struct vga *vga,
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uint64_t offset, int size);
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#endif /* _VGA_H_ */
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@@ -745,5 +745,22 @@ int virtio_set_modern_bar(struct virtio_base *base, bool use_notify_pio);
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/**
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* @}
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*/
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/* FIXME: Fix the assumption about the zero offset in virtio_pci_cap.
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* Should not export the internal virtio APIs.
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*/
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void virtio_common_cfg_write(struct pci_vdev *dev,
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uint64_t offset, int size, uint64_t value);
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void virtio_device_cfg_write(struct pci_vdev *dev,
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uint64_t offset, int size, uint64_t value);
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void virtio_notify_cfg_write(struct pci_vdev *dev,
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uint64_t offset, int size, uint64_t value);
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uint32_t virtio_common_cfg_read(
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struct pci_vdev *dev, uint64_t offset, int size);
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uint32_t virtio_isr_cfg_read(
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struct pci_vdev *dev, uint64_t offset, int size);
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uint32_t virtio_device_cfg_read(
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struct pci_vdev *dev, uint64_t offset, int size);
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int virtio_set_modern_pio_bar(
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struct virtio_base *base, int barnum);
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#endif /* _VIRTIO_H_ */
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@@ -53,6 +53,7 @@ struct vmctx {
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uint32_t lowmem_limit;
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uint64_t highmem_gpa_base;
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size_t lowmem;
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size_t fbmem;
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size_t biosmem;
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size_t highmem;
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char *baseaddr;
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@@ -64,6 +65,7 @@ struct vmctx {
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void *vpit;
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void *ioc_dev;
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void *tpm_dev;
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void *fb_base;
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/* BSP state. guest loader needs to fill it */
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struct acrn_vcpu_regs bsp_regs;
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