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hv:disable iommu snoop control to enable gvt-d by an option
If one of the enabled VT-d DMAR units doesn’t support snoop control, then bit 11 of leaf PET of EPT is not set, since the field is treated as reserved(0) by VT-d hardware implementations not supporting snoop control. GUP IOMMU doesn’t support snoop control, this patch add an option to disable iommu snoop control for gvt-d. v2 -> v3: * refine the MICRO name and description. Tracked-On: #4405 Signed-off-by: Junming Liu <junming.liu@intel.com> Reviewed-by: Wu Binbin <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -340,3 +340,10 @@ config MCE_ON_PSC_WORKAROUND_DISABLED
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conditionally applied to the models that may be affected by the issue. However,
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the software workaround has negative impact on performance. If all the guest OS
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kernels are trusted, this option may be set for performance.
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config IOMMU_ENFORCE_SNP
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bool "IOMMU enforce snoop behavior of DMA operation"
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default n
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help
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GPU IOMMU doesn't support snoop control capability,
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To enable gvt-d,disable IOMMU snoop control by default.
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@ -1263,7 +1263,17 @@ struct iommu_domain *create_iommu_domain(uint16_t vm_id, uint64_t translation_ta
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domain->trans_table_ptr = translation_table;
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domain->addr_width = addr_width;
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domain->is_tt_ept = true;
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#ifdef CONFIG_IOMMU_ENFORCE_SNP
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domain->iommu_snoop = true;
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#else
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/* TODO: GPU IOMMU doesn't have snoop control capbility,
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* so set domain->iommu_snoop false to enable gvt-d by default.
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* If want to refine iommu snoop control policy,
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* need to change domain->iommu_snoop dynamically.
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*/
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domain->iommu_snoop = false;
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#endif
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dev_dbg(DBG_LEVEL_IOMMU, "create domain [%d]: vm_id = %hu, ept@0x%x",
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vmid_to_domainid(domain->vm_id), domain->vm_id, domain->trans_table_ptr);
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