From 22a302599aa091528423968e38ab3f055ed66e3c Mon Sep 17 00:00:00 2001 From: Jian Jun Chen Date: Tue, 19 Jul 2022 10:02:31 +0800 Subject: [PATCH] hv: tlfs: fix the incorrect vLAPIC freq MSR When LAPIC timer is working in oneshot or periodic mode, OS uses initial counter register/current counter register to program a timer. Both initial counter and current counter depend on the LAPIC frequency. ACRN emulated vLAPIC timer based on the TSC. vLAPIC freq is the same as TSC freq. Tracked-On: #7876 Signed-off-by: Jian Jun Chen Reviewed-by: Zhao Yakui --- hypervisor/arch/x86/guest/hyperv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hypervisor/arch/x86/guest/hyperv.c b/hypervisor/arch/x86/guest/hyperv.c index 6cf171fef..949ba8095 100644 --- a/hypervisor/arch/x86/guest/hyperv.c +++ b/hypervisor/arch/x86/guest/hyperv.c @@ -212,8 +212,8 @@ hyperv_rdmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *rval) *rval = get_tsc_khz() * 1000UL; break; case HV_X64_MSR_APIC_FREQUENCY: - /* both KVM and XEN hardcode the APIC freq as 1GHz ... */ - *rval = 1000000000UL; + /* vLAPIC freq is the same as TSC freq */ + *rval = get_tsc_khz() * 1000UL; break; default: pr_err("hv: %s: unexpected MSR[0x%x] read", __func__, msr);