board_inspector: add interrupt pin routing and usage

This patch adds interrupt pin related information into the board XML,
including:

  * The PCI routing table in ACPI DSDT/SSDT are parsed and generated into
    the board XML as "interrupt_pin_routing" nodes.

  * IRQs encoded in _CRS directly are represented as resources of type
    "irq".

  * Interrupt lines (i.e. INTx#) of PCI devices are represented as
    resources of type "interrupt_pin". When the PCI routing table is
    available, the corresponding interrupt line is identified and
    represented as the "source" attribute of the resource node.

Due to the existence of vIOAPIC in ACRN VMs, the board inspector interprets
the \_PIC method with parameter 1 to inform the ACPI namespace that the
interrupt model should be in APIC mode.

v1 -> v2:
  * Remove the msi_enable variable which is defined but never used.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>

misc/config_tools/static_allocators/gpa.py

@@ -204,7 +204,7 @@ def get_devs_mem_passthrough(board_etree, scenario_etree):
 
 def get_pci_hole_native(board_etree):
     resources = board_etree.xpath(f"//bus[@type = 'pci']/device[@address]/resource[@type = 'memory' and @len != '0x0']")
-    resources_hostbridge =  board_etree.xpath("//bus[@address = '0x0']/resource[@type = 'memory' and @len != '0x0' and not(@id) and not(@width)]")
+    resources_hostbridge =  board_etree.xpath("//bus[@address = '0x0']/resource[@type = 'memory' and @len != '0x0' and not(starts-with(@id, 'bar')) and not(@width)]")
     low_mem = set()
     high_mem = set()
     for resource_hostbridge in resources_hostbridge: