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hv: no need to return error when inject GP

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GP fault is a normal case,no need to return error.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Mingqiang Chi 2018-07-10 13:08:24 +08:00 committed by lijinxia
parent 809eb9f6ca
commit 2686fe76bc
4 changed files with 12 additions and 13 deletions
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3
hypervisor/arch/x86/virq.c
View File

@ -290,11 +290,10 @@ void vcpu_inject_nmi(struct vcpu *vcpu)
vcpu_make_request(vcpu, ACRN_REQUEST_NMI);
}
int vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code)
void vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code)
{
vcpu_queue_exception(vcpu, IDT_GP, err_code);
vcpu_make_request(vcpu, ACRN_REQUEST_EXCP);
return 0;
}
int vcpu_inject_pf(struct vcpu *vcpu, uint64_t addr, uint32_t err_code)

8
hypervisor/arch/x86/vmexit.c
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@ -308,7 +308,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
val64 = exec_vmread(VMX_GUEST_CR4);
if ((val64 & CR4_OSXSAVE) == 0U) {
vcpu_inject_gp(vcpu, 0U);
return -1;
return 0;
}
idx = vcpu->arch_vcpu.cur_context;
@ -320,7 +320,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
/*to access XCR0,'rcx' should be 0*/
if (ctx_ptr->guest_cpu_regs.regs.rcx != 0UL) {
vcpu_inject_gp(vcpu, 0U);
return -1;
return 0;
}
val64 = ((ctx_ptr->guest_cpu_regs.regs.rax) & 0xffffffffUL) |
@ -329,7 +329,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
/*bit 0(x87 state) of XCR0 can't be cleared*/
if ((val64 & 0x01UL) == 0UL) {
vcpu_inject_gp(vcpu, 0U);
return -1;
return 0;
}
/*XCR0[2:1] (SSE state & AVX state) can't not be
@ -338,7 +338,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
**/
if (((val64 >> 1UL) & 0x3UL) == 0x2UL) {
vcpu_inject_gp(vcpu, 0U);
return -1;
return 0;
}
write_xcr(0, val64);

12
hypervisor/arch/x86/vmx.c
View File

@ -317,7 +317,7 @@ int vmx_wrmsr_pat(struct vcpu *vcpu, uint64_t value)
(PAT_FIELD_RSV_BITS & field) != 0U)) {
pr_err("invalid guest IA32_PAT: 0x%016llx", value);
vcpu_inject_gp(vcpu, 0U);
return -EINVAL;
return 0;
}
}
@ -365,7 +365,7 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
if ((cr0 & (cr0_always_off_mask | CR0_RESERVED_MASK)) != 0U) {
pr_err("Not allow to set always off / reserved bits for CR0");
vcpu_inject_gp(vcpu, 0U);
return -EINVAL;
return 0;
}
/* TODO: Check all invalid guest statuses according to the change of
@ -376,7 +376,7 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
if ((context->cr4 & CR4_PAE) == 0U) {
pr_err("Can't enable long mode when PAE disabled");
vcpu_inject_gp(vcpu, 0U);
return -EINVAL;
return 0;
}
/* Enable long mode */
pr_dbg("VMM: Enable long mode");
@ -403,7 +403,7 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
if ((cr0 & CR0_CD) == 0U && ((cr0 & CR0_NW) != 0U)) {
pr_err("not allow to set CR0.NW while clearing CR0.CD");
vcpu_inject_gp(vcpu, 0U);
return -EINVAL;
return 0;
}
/* No action if only CR0.NW is changed */
@ -500,14 +500,14 @@ int vmx_write_cr4(struct vcpu *vcpu, uint64_t cr4)
if((cr4 & cr4_always_off_mask) != 0U) {
pr_err("Not allow to set reserved/always off bits for CR4");
vcpu_inject_gp(vcpu, 0U);
return -EINVAL;
return 0;
}
/* Do NOT support nested guest */
if ((cr4 & CR4_VMXE) != 0U) {
pr_err("Nested guest not supported");
vcpu_inject_gp(vcpu, 0U);
return -EINVAL;
return 0;
}
/* Aways off bits and reserved bits has been filtered above */

2
hypervisor/include/arch/x86/irq.h
View File

@ -96,7 +96,7 @@ extern spurious_handler_t spurious_handler;
void vcpu_inject_extint(struct vcpu *vcpu);
void vcpu_inject_nmi(struct vcpu *vcpu);
int vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code);
void vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code);
int vcpu_inject_pf(struct vcpu *vcpu, uint64_t addr, uint32_t err_code);
void vcpu_make_request(struct vcpu *vcpu, int eventid);
int vcpu_queue_exception(struct vcpu *vcpu, uint32_t vector, uint32_t err_code);