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hv: move dm/hw/pci.c to hw/pci.c
This patch moves `dm/hw/pci.c` to `hw/pci.c` Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao
wenlingz
@@ -1,182 +0,0 @@
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/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <hypervisor.h>
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#include <pci.h>
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static spinlock_t pci_device_lock = {
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.head = 0U,
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.tail = 0U
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};
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static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
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{
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uint32_t addr = (uint32_t)bdf.value;
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addr <<= 8U;
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addr |= (offset | PCI_CFG_ENABLE);
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return addr;
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}
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uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
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{
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uint32_t addr;
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uint32_t val;
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spinlock_obtain(&pci_device_lock);
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addr = pci_pdev_calc_address(bdf, offset);
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/* Write address to ADDRESS register */
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pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
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/* Read result from DATA register */
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switch (bytes) {
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case 1U:
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val = (uint32_t)pio_read8((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
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break;
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case 2U:
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val = (uint32_t)pio_read16((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
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break;
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default:
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val = pio_read32((uint16_t)PCI_CONFIG_DATA);
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break;
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}
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spinlock_release(&pci_device_lock);
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return val;
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}
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void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint32_t addr;
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spinlock_obtain(&pci_device_lock);
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addr = pci_pdev_calc_address(bdf, offset);
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/* Write address to ADDRESS register */
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pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
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/* Write value to DATA register */
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switch (bytes) {
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case 1U:
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pio_write8((uint8_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
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break;
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case 2U:
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pio_write16((uint16_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
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break;
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default:
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pio_write32(val, (uint16_t)PCI_CONFIG_DATA);
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break;
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}
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spinlock_release(&pci_device_lock);
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}
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/* enable: 1: enable INTx; 0: Disable INTx */
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable)
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{
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uint32_t cmd, new_cmd;
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/* Set or clear the INTXDIS bit in COMMAND register */
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cmd = pci_pdev_read_cfg(bdf, PCIR_COMMAND, 2U);
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if (enable) {
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new_cmd = cmd & ~PCIM_CMD_INTxDIS;
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} else {
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new_cmd = cmd | PCIM_CMD_INTxDIS;
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}
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if ((cmd ^ new_cmd) != 0U) {
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pci_pdev_write_cfg(bdf, PCIR_COMMAND, 0x2U, new_cmd);
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}
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}
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#define BUS_SCAN_SKIP 0U
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#define BUS_SCAN_PENDING 1U
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#define BUS_SCAN_COMPLETE 2U
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void pci_scan_bus(pci_enumeration_cb cb_func, void *cb_data)
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{
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union pci_bdf pbdf;
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uint8_t hdr_type, secondary_bus, dev, func;
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uint32_t bus, val;
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uint8_t bus_to_scan[PCI_BUSMAX + 1] = { BUS_SCAN_SKIP };
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/* start from bus 0 */
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bus_to_scan[0U] = BUS_SCAN_PENDING;
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for (bus = 0U; bus <= PCI_BUSMAX; bus++) {
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if (bus_to_scan[bus] != BUS_SCAN_PENDING) {
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continue;
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}
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bus_to_scan[bus] = BUS_SCAN_COMPLETE;
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pbdf.bits.b = (uint8_t)bus;
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for (dev = 0U; dev <= PCI_SLOTMAX; dev++) {
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pbdf.bits.d = dev;
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for (func = 0U; func <= PCI_FUNCMAX; func++) {
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pbdf.bits.f = func;
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val = pci_pdev_read_cfg(pbdf, PCIR_VENDOR, 4U);
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if ((val == 0xFFFFFFFFU) || (val == 0x0U)) {
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/* If function 0 is not implemented, skip to next device */
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if (func == 0U) {
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break;
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}
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/* continue scan next function */
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continue;
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}
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/* if it is debug uart, hide it from SOS */
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if (is_pci_dbg_uart(pbdf)) {
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pr_info("hide pci uart dev: (%x:%x:%x)", pbdf.bits.b, pbdf.bits.d, pbdf.bits.f);
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continue;
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}
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if (cb_func != NULL) {
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cb_func(pbdf.value, cb_data);
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}
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hdr_type = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_HDRTYPE, 1U);
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if ((hdr_type & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
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/* Secondary bus to be scanned */
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secondary_bus = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_SECBUS_1, 1U);
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if (bus_to_scan[secondary_bus] != BUS_SCAN_SKIP) {
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pr_err("%s, bus %d may be downstream of different PCI bridges", secondary_bus);
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} else {
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bus_to_scan[secondary_bus] = BUS_SCAN_PENDING;
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}
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}
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}
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}
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}
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}
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