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HV: RDT: clean up RDT code

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This commit makes some RDT code cleanup, mainling including:
- remove the clos_mask and mba_delay validation check in setup_res_clos_msr(), the check will be done in pre-build;
- rename platform_clos_num to valid_clos_num, which is set as the minimal clos_mas of all enabled RDT resouces;
- init the platform_clos_array in the res_cap_info[] definition;
- remove the unnecessary return values and return value check.

Tracked-On: #4604
Signed-off-by: Yan, Like <like.yan@intel.com>
This commit is contained in:
Yan, Like 2020-04-29 22:40:39 +08:00 committed by wenlingz
parent f774ee1fba
commit 277c668b04
4 changed files with 51 additions and 88 deletions
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4
hypervisor/arch/x86/configs/vm_config.c
View File

@ -103,9 +103,9 @@ static bool check_vm_clos_config(uint16_t vm_id)
struct acrn_vm_config *vm_config = get_vm_config(vm_id); struct acrn_vm_config *vm_config = get_vm_config(vm_id);
for (i = 0U; i < vm_config->vcpu_num; i++) { for (i = 0U; i < vm_config->vcpu_num; i++) {
if (vm_config->clos[i] >= platform_clos_num) { if (vm_config->clos[i] >= valid_clos_num) {
pr_err("vm%u: vcpu%u clos(%u) exceed the max clos(%u).", pr_err("vm%u: vcpu%u clos(%u) exceed the max clos(%u).",
vm_id, i, vm_config->clos[i], platform_clos_num); vm_id, i, vm_config->clos[i], valid_clos_num);
ret = false; ret = false;
break; break;
} }

9
hypervisor/arch/x86/cpu.c
View File

@ -167,10 +167,7 @@ void init_pcpu_pre(bool is_bsp)
} }
#ifdef CONFIG_RDT_ENABLED #ifdef CONFIG_RDT_ENABLED
ret = init_rdt_cap_info(); init_rdt_cap_info();
if (ret != 0) {
panic("Platform RDT info is incorrect!");
}
#endif #endif
/* NOTE: this must call after MMCONFIG is parsed in init_vboot and before APs are INIT. /* NOTE: this must call after MMCONFIG is parsed in init_vboot and before APs are INIT.
@ -288,9 +285,7 @@ void init_pcpu_post(uint16_t pcpu_id)
init_sched(pcpu_id); init_sched(pcpu_id);
#ifdef CONFIG_RDT_ENABLED #ifdef CONFIG_RDT_ENABLED
if (!setup_clos(pcpu_id)) { setup_clos(pcpu_id);
panic("CLOS resource MSRs setup incorrectly!");
}
#endif #endif
enable_smep(); enable_smep();

120
hypervisor/arch/x86/rdt.c
View File

@ -17,6 +17,14 @@
#include <vm_config.h> #include <vm_config.h>
#include <msr.h> #include <msr.h>
const uint16_t hv_clos = 0U;
/* RDT features can support different numbers of CLOS. Set the lowers numerical
* clos value (valid_clos_num) that is common between the resources as
* each resource's clos max value to have consistent allocation.
*/
uint16_t valid_clos_num = MAX_PLATFORM_CLOS_NUM;
#ifdef CONFIG_RDT_ENABLED
static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = { static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
[RDT_RESOURCE_L3] = { [RDT_RESOURCE_L3] = {
.res.cache = { .res.cache = {
@ -26,7 +34,7 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
.clos_max = 0U, .clos_max = 0U,
.res_id = RDT_RESID_L3, .res_id = RDT_RESID_L3,
.msr_base = MSR_IA32_L3_MASK_BASE, .msr_base = MSR_IA32_L3_MASK_BASE,
.platform_clos_array = NULL .platform_clos_array = platform_l3_clos_array,
}, },
[RDT_RESOURCE_L2] = { [RDT_RESOURCE_L2] = {
.res.cache = { .res.cache = {
@ -36,7 +44,7 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
.clos_max = 0U, .clos_max = 0U,
.res_id = RDT_RESID_L2, .res_id = RDT_RESID_L2,
.msr_base = MSR_IA32_L2_MASK_BASE, .msr_base = MSR_IA32_L2_MASK_BASE,
.platform_clos_array = NULL .platform_clos_array = platform_l2_clos_array,
}, },
[RDT_RESOURCE_MBA] = { [RDT_RESOURCE_MBA] = {
.res.membw = { .res.membw = {
@ -46,17 +54,13 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
.clos_max = 0U, .clos_max = 0U,
.res_id = RDT_RESID_MBA, .res_id = RDT_RESID_MBA,
.msr_base = MSR_IA32_MBA_MASK_BASE, .msr_base = MSR_IA32_MBA_MASK_BASE,
.platform_clos_array = NULL .platform_clos_array = platform_mba_clos_array,
}, },
}; };
const uint16_t hv_clos = 0U;
/* RDT features can support different numbers of CLOS. Set the lowers numerical
* clos value (platform_clos_num) that is common between the resources as
* each resource's clos max value to have consistent allocation.
*/
const uint16_t platform_clos_num = MAX_PLATFORM_CLOS_NUM;
#ifdef CONFIG_RDT_ENABLED /*
* @pre res == RDT_RESOURCE_L3 || res == RDT_RESOURCE_L2
*/
static void rdt_read_cat_capability(int res) static void rdt_read_cat_capability(int res)
{ {
uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U; uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
@ -87,11 +91,13 @@ static void rdt_read_mba_capability(int res)
res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1U; res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1U;
} }
int32_t init_rdt_cap_info(void) /*
* @pre valid_clos_num > 0U
*/
void init_rdt_cap_info(void)
{ {
uint8_t i; uint8_t i;
uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U; uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
int32_t ret = 0;
if (pcpu_has_cap(X86_FEATURE_RDT_A)) { if (pcpu_has_cap(X86_FEATURE_RDT_A)) {
cpuid_subleaf(CPUID_RDT_ALLOCATION, 0U, &eax, &ebx, &ecx, &edx); cpuid_subleaf(CPUID_RDT_ALLOCATION, 0U, &eax, &ebx, &ecx, &edx);
@ -112,85 +118,48 @@ int32_t init_rdt_cap_info(void)
} }
for (i = 0U; i < RDT_NUM_RESOURCES; i++) { for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
/* If clos_max == 0, the resource is not supported /* If clos_max == 0, the resource is not supported. Set the
* so skip checking and updating the clos_max * valid_clos_num as the minimal clos_max of all support rdt resource.
*/ */
if (res_cap_info[i].clos_max > 0U) { if (res_cap_info[i].clos_max > 0U) {
if ((platform_clos_num == 0U) || (res_cap_info[i].clos_max < platform_clos_num)) { if (res_cap_info[i].clos_max < valid_clos_num) {
pr_err("Invalid Res_ID %d clos max:platform_clos_max=%d, res_clos_max=%d\n", valid_clos_num = res_cap_info[i].clos_max;
res_cap_info[i].res_id, platform_clos_num, res_cap_info[i].clos_max);
ret = -EINVAL;
break;
}
/*Store user configured platform clos mask and MSR in the rdt_info struct*/
if (res_cap_info[i].res_id == RDT_RESID_L3) {
res_cap_info[i].platform_clos_array = platform_l3_clos_array;
} else if (res_cap_info[i].res_id == RDT_RESID_L2) {
res_cap_info[i].platform_clos_array = platform_l2_clos_array;
} else if (res_cap_info[i].res_id == RDT_RESID_MBA) {
res_cap_info[i].platform_clos_array = platform_mba_clos_array;
} else {
res_cap_info[i].platform_clos_array = NULL;
} }
} }
} }
} }
return ret;
} }
/* /*
* @pre res < RDT_NUM_RESOURCES * @pre res < RDT_NUM_RESOURCES
* @pre res_clos_info[i].mba_delay <= res_cap_info[res].res.membw.mba_max
* @pre length of res_clos_info[i].clos_mask <= cbm_len && all 1's in clos_mask is continuous
*/ */
static bool setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_clos_info *res_clos_info) static void setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_clos_info *res_clos_info)
{ {
bool ret = true;
uint16_t i; uint16_t i;
uint32_t msr_index; uint32_t msr_index;
uint64_t val; uint64_t val;
for (i = 0U; i < platform_clos_num; i++) { for (i = 0U; i < valid_clos_num; i++) {
switch (res) { switch (res) {
case RDT_RESOURCE_L3: case RDT_RESOURCE_L3:
case RDT_RESOURCE_L2: case RDT_RESOURCE_L2:
if ((fls32(res_clos_info->clos_mask) >= res_cap_info[res].res.cache.cbm_len) || val = (uint64_t)res_clos_info[i].clos_mask;
(res_clos_info->msr_index != (res_cap_info[res].msr_base + i))) {
ret = false;
pr_err("Fix CLOS %d mask=0x%x and(/or) MSR index=0x%x for Res_ID %d in board.c",
i, res_clos_info->clos_mask, res_clos_info->msr_index, res);
} else {
val = (uint64_t)res_clos_info->clos_mask;
}
break; break;
case RDT_RESOURCE_MBA: case RDT_RESOURCE_MBA:
if ((res_clos_info->mba_delay > res_cap_info[res].res.membw.mba_max) || val = (uint64_t)res_clos_info[i].mba_delay;
(res_clos_info->msr_index != (res_cap_info[res].msr_base + i))) {
ret = false;
pr_err("Fix CLOS %d delay=0x%x and(/or) MSR index=0x%x for Res_ID %d in board.c",
i, res_clos_info->mba_delay, res_clos_info->msr_index, res);
} else {
val = (uint64_t)res_clos_info->mba_delay;
}
break; break;
default: default:
ret = false;
ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res); ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);
break;
}
if (!ret) {
break;
} }
msr_index = res_clos_info->msr_index; msr_index = res_clos_info->msr_index;
msr_write_pcpu(msr_index, val, pcpu_id); msr_write_pcpu(msr_index, val, pcpu_id);
res_clos_info++;
} }
return ret;
} }
bool setup_clos(uint16_t pcpu_id) void setup_clos(uint16_t pcpu_id)
{ {
bool ret = true;
uint16_t i; uint16_t i;
for (i = 0U; i < RDT_NUM_RESOURCES; i++) { for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
@ -198,18 +167,12 @@ bool setup_clos(uint16_t pcpu_id)
* so skip setting up resource MSR. * so skip setting up resource MSR.
*/ */
if (res_cap_info[i].clos_max > 0U) { if (res_cap_info[i].clos_max > 0U) {
ret = setup_res_clos_msr(pcpu_id, i, res_cap_info[i].platform_clos_array); setup_res_clos_msr(pcpu_id, i, res_cap_info[i].platform_clos_array);
if (!ret)
break;
} }
} }
if (ret) { /* set hypervisor RDT resource clos */
/* set hypervisor RDT resource clos */ msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2pqr_msr(hv_clos), pcpu_id);
msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2pqr_msr(hv_clos), pcpu_id);
}
return ret;
} }
uint64_t clos2pqr_msr(uint16_t clos) uint64_t clos2pqr_msr(uint16_t clos)
@ -221,13 +184,6 @@ uint64_t clos2pqr_msr(uint16_t clos)
return pqr_assoc; return pqr_assoc;
} }
#else
uint64_t clos2pqr_msr(uint16_t clos)
{
(void)(clos);
return 0UL;
}
#endif
bool is_platform_rdt_capable(void) bool is_platform_rdt_capable(void)
{ {
@ -241,3 +197,15 @@ bool is_platform_rdt_capable(void)
return ret; return ret;
} }
#else
uint64_t clos2pqr_msr(uint16_t clos)
{
(void)(clos);
return 0UL;
}
bool is_platform_rdt_capable(void)
{
return false;
}
#endif

6
hypervisor/include/arch/x86/rdt.h
View File

@ -21,7 +21,7 @@ enum {
#define RDT_RESID_MBA 3U #define RDT_RESID_MBA 3U
extern const uint16_t hv_clos; extern const uint16_t hv_clos;
extern const uint16_t platform_clos_num; extern uint16_t valid_clos_num;
/* The intel Resource Director Tech(RDT) based Allocation Tech support */ /* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_info { struct rdt_info {
@ -42,8 +42,8 @@ struct rdt_info {
struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/ struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/
}; };
int32_t init_rdt_cap_info(void); void init_rdt_cap_info(void);
bool setup_clos(uint16_t pcpu_id); void setup_clos(uint16_t pcpu_id);
uint64_t clos2pqr_msr(uint16_t clos); uint64_t clos2pqr_msr(uint16_t clos);
bool is_platform_rdt_capable(void); bool is_platform_rdt_capable(void);