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dm: Add PCI IDS for EHL/TGL/ADL in GPU passthrough
Add PCI IDS for ElkhartLake/TigerLake/AlderLake in GPU DSM and OpRegion passthrough. Tracked-On: #6270 Signed-off-by: Sun Peng <peng.p.sun@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
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@ -438,8 +438,34 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
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gpu_opregion_hpa = opregion_phys & PCIM_ASLS_OPREGION_MASK;
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switch (device) {
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case INTEL_ELKHARTLAKE:
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case INTEL_TIGERLAKE:
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/* ElkhartLake */
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case 0x4500:
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case 0x4541:
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case 0x4551:
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case 0x4571:
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/* TigerLake */
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case 0x9a40:
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case 0x9a49:
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case 0x9a59:
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case 0x9a60:
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case 0x9a68:
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case 0x9a70:
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case 0x9a78:
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case 0x9ac0:
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case 0x9ac9:
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case 0x9ad9:
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case 0x9af8:
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/* AlderLake */
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case 0x4680:
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case 0x4681:
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case 0x4682:
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case 0x4683:
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case 0x4690:
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case 0x4691:
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case 0x4692:
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case 0x4693:
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case 0x4698:
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case 0x4699:
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/* BDSM register has 64 bits.
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* bits 63:20 contains the base address of stolen memory
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*/
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@ -1066,8 +1066,6 @@
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#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */
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/* Graphics definitions */
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#define INTEL_ELKHARTLAKE 0x4571
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#define INTEL_TIGERLAKE 0x9a49
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#define PCIR_BDSM 0x5C /* BDSM graphics base data of stolen memory register */
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#define PCIR_GEN11_BDSM_DW0 0xC0
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#define PCIR_GEN11_BDSM_DW1 0xC4
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