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dm: add support of high MMIO mapping

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1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.

Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Jian Jun Chen
2019-02-25 16:28:14 +08:00
committed by wenlingz
parent 32925c10bd
commit 29b1ebcd43
9 changed files with 34 additions and 26 deletions
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3
devicemodel/hw/pci/core.c
View File

@@ -97,9 +97,6 @@ SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
#define PCI_EMUL_MEMBASE64 0x100000000UL
#define PCI_EMUL_MEMLIMIT64 0x140000000UL
static struct pci_vdev_ops *pci_emul_finddev(char *name);
static void pci_lintr_route(struct pci_vdev *dev);
static void pci_lintr_update(struct pci_vdev *dev);

4
devicemodel/hw/pci/virtio/vhost.c
View File

@@ -523,10 +523,10 @@ vhost_set_mem_table(struct vhost_dev *vdev)
}
if (ctx->highmem > 0) {
mem->regions[nregions].guest_phys_addr = 4*GB;
mem->regions[nregions].guest_phys_addr = ctx->highmem_gpa_base;
mem->regions[nregions].memory_size = ctx->highmem;
mem->regions[nregions].userspace_addr =
(uintptr_t)(ctx->baseaddr + 4*GB);
(uintptr_t)(ctx->baseaddr + ctx->highmem_gpa_base);
DPRINTF("[%d][0x%llx -> 0x%llx, 0x%llx]\n",
nregions,
mem->regions[nregions].guest_phys_addr,