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dm: add support of high MMIO mapping

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1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.

Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Jian Jun Chen
2019-02-25 16:28:14 +08:00
committed by wenlingz
parent 32925c10bd
commit 29b1ebcd43
9 changed files with 34 additions and 26 deletions
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3
devicemodel/include/pci_core.h
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@@ -38,6 +38,9 @@
#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
#define PCI_BDF(b, d, f) (((b & 0xFF) << 8) | ((d & 0x1F) << 3) | ((f & 0x7)))
#define PCI_EMUL_MEMBASE64 0x100000000UL
#define PCI_EMUL_MEMLIMIT64 0x140000000UL
struct vmctx;
struct pci_vdev;
struct memory_region;