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dm: add support of high MMIO mapping

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1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.

Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Jian Jun Chen
2019-02-25 16:28:14 +08:00
committed by wenlingz
parent 32925c10bd
commit 29b1ebcd43
9 changed files with 34 additions and 26 deletions
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4
devicemodel/include/sw_load.h
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@@ -38,9 +38,9 @@
#define E820_TYPE_ACPI_NVS 4 /* EFI 10 */
#define E820_TYPE_UNUSABLE 5 /* EFI 8 */
#define NUM_E820_ENTRIES 6
#define NUM_E820_ENTRIES 7
#define LOWRAM_E820_ENTRIES 2
#define HIGHRAM_E820_ENTRIES 5
#define HIGHRAM_E820_ENTRIES 6
/* Defines a single entry in an E820 memory map. */
struct e820_entry {