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hv: vtd: export iommu_flush_cache

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VT-d shares the EPT tables as the second level translation tables.
For the IOMMUs that don't support page-walk coherecy, cpu cache should
be flushed for the IOMMU EPT entries that are modified.

For the current implementation, EPT tables for translating from GPA to HPA
for EPT/IOMMU are not modified after VM is created, so cpu cache invlidation is
done once per VM before starting execution of VM.
However, this may be changed, runtime EPT modification is possible.

When cpu cache of EPT entries is invalidated when modification, there is no need
invalidate cpu cache globally per VM.

This patch exports iommu_flush_cache for EPT entry cache invlidation operations.
- IOMMUs share the same copy of EPT table, cpu cache should be flushed if any of
  the IOMMU active doesn't support page-walk coherency.
- In the context of ACRN, GPA to HPA mapping relationship is not changed after
  VM created, skip flushing iotlb to avoid potential performance penalty.

Tracked-On: #3607
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Binbin Wu
2019-07-01 12:23:15 +08:00
committed by ACRN System Integration
parent 826aaf7bab
commit 2abd8b34ef
3 changed files with 29 additions and 15 deletions
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8
hypervisor/include/arch/x86/mmu.h
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@@ -102,8 +102,8 @@ enum _page_table_level {
#define PAGE_SIZE_2M MEM_2M
#define PAGE_SIZE_1G MEM_1G
void sanitize_pte_entry(uint64_t *ptep);
void sanitize_pte(uint64_t *pt_page);
void sanitize_pte_entry(uint64_t *ptep, const struct memory_ops *mem_ops);
void sanitize_pte(uint64_t *pt_page, const struct memory_ops *mem_ops);
/**
* @brief MMU paging enable
*
@@ -176,12 +176,12 @@ static inline void cache_flush_invalidate_all(void)
asm volatile (" wbinvd\n" : : : "memory");
}
static inline void clflush(volatile void *p)
static inline void clflush(const volatile void *p)
{
asm volatile ("clflush (%0)" :: "r"(p));
}
static inline void clflushopt(volatile void *p)
static inline void clflushopt(const volatile void *p)
{
asm volatile ("clflushopt (%0)" :: "r"(p));
}