hv: vlapic: fix "Procedure has more than one exit point"

IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Reduce the count of the "return entries".
Fix the violations which is comply with the cases list below:
1.Function has 2 return entries.
2.The first return entry is used to return the error code of
checking variable whether is valid.

Fix the violations in "if else" format.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/arch/x86/guest/vlapic.c

@@ -308,15 +308,15 @@ set_expiration(struct acrn_vlapic *vlapic)
 	struct vlapic_timer *vtimer;
 	struct hv_timer *timer;
 	uint32_t tmicr, divisor_shift;
+	bool ret;
 
 	vtimer = &vlapic->vtimer;
 	tmicr = vtimer->tmicr;
 	divisor_shift = vtimer->divisor_shift;
 
 	if ((tmicr == 0U) || (divisor_shift > 8U)) {
-		return false;
+		ret = false;
-	}
+	} else {
-
 		delta = tmicr << divisor_shift;
 		timer = &vtimer->timer;
 
@@ -324,8 +324,9 @@ set_expiration(struct acrn_vlapic *vlapic)
 			timer->period_in_cycle = delta;
 		}
 		timer->fire_tsc = now + delta;
-
+		ret = true;
-	return true;
+	}
+	return ret;
 }
 
 static void vlapic_update_lvtt(struct acrn_vlapic *vlapic,
@@ -390,10 +391,7 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
 	struct lapic_regs *lapic;
 	struct vlapic_timer *vtimer;
 
-	if (vlapic_lvtt_tsc_deadline(vlapic)) {
+	if (!vlapic_lvtt_tsc_deadline(vlapic)) {
-		return;
-	}
-
 		lapic = &(vlapic->apic_page);
 		vtimer = &vlapic->vtimer;
 		vtimer->tmicr = lapic->icr_timer.v;
@@ -407,15 +405,19 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
 			(void)add_timer(&vtimer->timer);
 		}
 	}
+}
 
 static uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic)
 {
+	uint64_t ret;
 	if (!vlapic_lvtt_tsc_deadline(vlapic)) {
-		return 0;
+		ret = 0UL;
+	} else {
+		ret = (vlapic->vtimer.timer.fire_tsc == 0UL) ? 0UL :
+			vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE];
 	}
 
-	return (vlapic->vtimer.timer.fire_tsc == 0UL) ? 0UL :
+	return ret;
-			vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE];
 
 }
 
@@ -425,10 +427,7 @@ static void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic,
 	struct hv_timer *timer;
 	uint64_t val = val_arg;
 
-	if (!vlapic_lvtt_tsc_deadline(vlapic)) {
+	if (vlapic_lvtt_tsc_deadline(vlapic)) {
-		return;
-	}
-
 		vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE] = val;
 
 		timer = &vlapic->vtimer.timer;
@@ -447,6 +446,7 @@ static void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic,
 			timer->fire_tsc = 0UL;
 		}
 	}
+}
 
 static void
 vlapic_esr_write_handler(struct acrn_vlapic *vlapic)
@@ -920,9 +920,7 @@ vlapic_set_error(struct acrn_vlapic *vlapic, uint32_t mask)
 	uint32_t lvt;
 
 	vlapic->esr_pending |= mask;
-	if (vlapic->esr_firing != 0) {
+	if (vlapic->esr_firing == 0) {
-		return;
-	}
 		vlapic->esr_firing = 1;
 
 		/* The error LVT always uses the fixed delivery mode. */
@@ -930,6 +928,7 @@ vlapic_set_error(struct acrn_vlapic *vlapic, uint32_t mask)
 		vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED);
 		vlapic->esr_firing = 0;
 	}
+}
 /*
  * @pre vector <= 255
  */
@@ -1151,13 +1150,12 @@ vlapic_set_cr8(struct acrn_vlapic *vlapic, uint64_t val)
 	if ((val & ~0xfUL) != 0U) {
 		struct acrn_vcpu *vcpu = vlapic->vcpu;
 		vcpu_inject_gp(vcpu, 0U);
-		return;
+	} else {
-	}
-
 		/* It is safe to narrow val as the higher 60 bits are 0s. */
 		tpr = (uint32_t)val << 4U;
 		vlapic_set_tpr(vlapic, tpr);
 	}
+}
 
 uint64_t
 vlapic_get_cr8(const struct acrn_vlapic *vlapic)
@@ -1589,11 +1587,8 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
 	dev_dbg(ACRN_DBG_LAPIC, "vlapic write offset %#x, data %#lx",
 		offset, data);
 
-	if (offset > sizeof(*lapic)) {
-		return 0;
-	}
-
 	retval = 0;
+	if (offset <= sizeof(*lapic)) {
 		switch (offset) {
 		case APIC_OFFSET_ID:
 			/* Force APIC ID as read only */
@@ -1673,6 +1668,7 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
 			/* Read only */
 			break;
 		}
+	}
 
 	return retval;
 }
@@ -1808,8 +1804,7 @@ vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest, bool phys,
 			(delmode != IOAPIC_RTE_DELEXINT)) {
 		dev_dbg(ACRN_DBG_LAPIC,
 			"vlapic intr invalid delmode %#x", delmode);
-		return;
+	} else {
-	}
 		lowprio = (delmode == IOAPIC_RTE_DELLOPRI) || rh;
 
 		/*
@@ -1836,18 +1831,22 @@ vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest, bool phys,
 			}
 		}
 	}
+}
 
 bool
 vlapic_enabled(const struct acrn_vlapic *vlapic)
 {
+	bool ret;
 	const struct lapic_regs *lapic = &(vlapic->apic_page);
 
 	if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0UL) &&
 			((lapic->svr.v & APIC_SVR_ENABLE) != 0U)) {
-		return true;
+		ret = true;
 	} else {
-		return false;
+	        ret = false;
 	}
+
+	return ret;
 }
 
 static void
@@ -1910,9 +1909,7 @@ vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
 		dev_dbg(ACRN_DBG_LAPIC,
 			"Ignoring level trigger-mode for delivery-mode %u",
 			delmode);
-		return;
+	} else {
-	}
-
 		/* NOTE
 		 * We don't check whether the vcpu is in the dest here. That means
 		 * all vcpus of vm will do tmr update.
@@ -1923,6 +1920,7 @@ vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
 		dev_dbg(ACRN_DBG_LAPIC, "vector %u set to level-triggered", vector);
 		vlapic_set_tmr(vlapic, vector, level);
 	}
+}
 
 /*
  *  @pre vcpu != NULL
@@ -1938,13 +1936,12 @@ vlapic_set_intr(struct acrn_vcpu *vcpu, uint32_t vector, bool level)
 		vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR);
 		dev_dbg(ACRN_DBG_LAPIC,
 		    "vlapic ignoring interrupt to vector %u", vector);
-		return;
+	} else {
-	}
-
 		if (vlapic_set_intr_ready(vlapic, vector, level) != 0) {
 			vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
 		}
 	}
+}
 
 /**
  * @brief Triggers LAPIC local interrupt(LVT).
@@ -1959,7 +1956,7 @@ vlapic_set_intr(struct acrn_vcpu *vcpu, uint32_t vector, bool level)
  *
  * @pre vm != NULL
  */
-int
+int32_t
 vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
 {
 	struct acrn_vlapic *vlapic;
@@ -1968,9 +1965,8 @@ vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
 	uint16_t vcpu_id = vcpu_id_arg;
 
 	if ((vcpu_id != BROADCAST_CPU_ID) && (vcpu_id >= vm->hw.created_vcpus)) {
-		return -EINVAL;
+	        error = -EINVAL;
-	}
+	} else {
-
 		if (vcpu_id == BROADCAST_CPU_ID) {
 			dmask = vm_active_cpus(vm);
 		} else {
@@ -1986,6 +1982,7 @@ vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
 				}
 			}
 		}
+	}
 
 	return error;
 }
@@ -2002,20 +1999,17 @@ vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
  *
  * @pre vm != NULL
  */
-int
+int32_t
 vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg)
 {
 	uint32_t delmode, vec;
 	uint32_t dest;
 	bool phys, rh;
+	int32_t ret;
 
 	dev_dbg(ACRN_DBG_LAPIC, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
 
-	if ((addr & MSI_ADDR_MASK) != MSI_ADDR_BASE) {
+	if ((addr & MSI_ADDR_MASK) == MSI_ADDR_BASE) {
-		dev_dbg(ACRN_DBG_LAPIC, "lapic MSI invalid addr %#lx", addr);
-		return -1;
-	}
-
 		/*
 		 * Extract the x86-specific fields from the MSI addr/msg
 		 * params according to the Intel Arch spec, Vol3 Ch 10.
@@ -2038,7 +2032,13 @@ vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg)
 			phys ? "physical" : "logical", dest, vec);
 
 		vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec, rh);
-	return 0;
+		ret = 0;
+	} else {
+		dev_dbg(ACRN_DBG_LAPIC, "lapic MSI invalid addr %#lx", addr);
+	        ret = -1;
+	}
+
+	return ret;
 }
 
 /* interrupt context */
@@ -2063,11 +2063,14 @@ static void vlapic_timer_expired(void *data)
 
 static inline bool is_x2apic_enabled(const struct acrn_vlapic *vlapic)
 {
+	bool ret;
 	if ((vlapic_get_apicbase(vlapic) & APICBASE_X2APIC) == 0UL) {
-		return false;
+		ret = false;
 	} else {
-		return true;
+	        ret = true;
 	}
+
+	return ret;
 }
 
 static inline  uint32_t x2apic_msr_to_regoff(uint32_t msr)
@@ -2379,10 +2382,7 @@ vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
 	struct lapic_reg *irr = NULL;
 
 	pir_desc = &(vlapic->pir_desc);
-	if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) != 1UL) {
+	if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) == 1UL) {
-		return;
-	}
-
 		pirval = 0UL;
 		lapic = &(vlapic->apic_page);
 		irr = &lapic->irr[0];
@@ -2432,6 +2432,7 @@ vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
 			}
 		}
 	}
+}
 
 int apic_access_vmexit_handler(struct acrn_vcpu *vcpu)
 {

hypervisor/include/arch/x86/guest/vlapic.h

@@ -231,7 +231,7 @@ vlapic_intr_edge(struct acrn_vcpu *vcpu, uint32_t vector)
  *
  * @pre vm != NULL
  */
-int vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector);
+int32_t vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector);
 
 /**
  * @brief Inject MSI to target VM.
@@ -245,7 +245,7 @@ int vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vec
  *
  * @pre vm != NULL
  */
-int vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg);
+int32_t vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg);
 
 void vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest,
 		bool phys, uint32_t delmode, uint32_t vec, bool rh);