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https://github.com/projectacrn/acrn-hypervisor.git
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hv: vlapic: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule. Reduce the count of the "return entries". Fix the violations which is comply with the cases list below: 1.Function has 2 return entries. 2.The first return entry is used to return the error code of checking variable whether is valid. Fix the violations in "if else" format. Tracked-On: #861 Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
lijinxia
parent
3d1332f392
commit
2afa7173ef
@ -308,15 +308,15 @@ set_expiration(struct acrn_vlapic *vlapic)
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struct vlapic_timer *vtimer;
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struct hv_timer *timer;
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uint32_t tmicr, divisor_shift;
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bool ret;
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vtimer = &vlapic->vtimer;
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tmicr = vtimer->tmicr;
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divisor_shift = vtimer->divisor_shift;
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if ((tmicr == 0U) || (divisor_shift > 8U)) {
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return false;
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}
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ret = false;
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} else {
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delta = tmicr << divisor_shift;
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timer = &vtimer->timer;
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@ -324,8 +324,9 @@ set_expiration(struct acrn_vlapic *vlapic)
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timer->period_in_cycle = delta;
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}
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timer->fire_tsc = now + delta;
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return true;
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ret = true;
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}
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return ret;
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}
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static void vlapic_update_lvtt(struct acrn_vlapic *vlapic,
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@ -390,10 +391,7 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic;
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struct vlapic_timer *vtimer;
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if (vlapic_lvtt_tsc_deadline(vlapic)) {
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return;
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}
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if (!vlapic_lvtt_tsc_deadline(vlapic)) {
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lapic = &(vlapic->apic_page);
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vtimer = &vlapic->vtimer;
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vtimer->tmicr = lapic->icr_timer.v;
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@ -407,15 +405,19 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
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(void)add_timer(&vtimer->timer);
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}
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}
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}
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static uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic)
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{
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uint64_t ret;
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if (!vlapic_lvtt_tsc_deadline(vlapic)) {
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return 0;
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ret = 0UL;
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} else {
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ret = (vlapic->vtimer.timer.fire_tsc == 0UL) ? 0UL :
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vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE];
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}
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return (vlapic->vtimer.timer.fire_tsc == 0UL) ? 0UL :
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vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE];
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return ret;
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}
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@ -425,10 +427,7 @@ static void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic,
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struct hv_timer *timer;
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uint64_t val = val_arg;
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if (!vlapic_lvtt_tsc_deadline(vlapic)) {
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return;
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}
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if (vlapic_lvtt_tsc_deadline(vlapic)) {
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vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE] = val;
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timer = &vlapic->vtimer.timer;
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@ -447,6 +446,7 @@ static void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic,
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timer->fire_tsc = 0UL;
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}
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}
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}
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static void
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vlapic_esr_write_handler(struct acrn_vlapic *vlapic)
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@ -920,9 +920,7 @@ vlapic_set_error(struct acrn_vlapic *vlapic, uint32_t mask)
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uint32_t lvt;
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vlapic->esr_pending |= mask;
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if (vlapic->esr_firing != 0) {
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return;
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}
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if (vlapic->esr_firing == 0) {
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vlapic->esr_firing = 1;
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/* The error LVT always uses the fixed delivery mode. */
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@ -930,6 +928,7 @@ vlapic_set_error(struct acrn_vlapic *vlapic, uint32_t mask)
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vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED);
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vlapic->esr_firing = 0;
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}
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}
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/*
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* @pre vector <= 255
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*/
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@ -1151,13 +1150,12 @@ vlapic_set_cr8(struct acrn_vlapic *vlapic, uint64_t val)
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if ((val & ~0xfUL) != 0U) {
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struct acrn_vcpu *vcpu = vlapic->vcpu;
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vcpu_inject_gp(vcpu, 0U);
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return;
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}
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} else {
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/* It is safe to narrow val as the higher 60 bits are 0s. */
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tpr = (uint32_t)val << 4U;
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vlapic_set_tpr(vlapic, tpr);
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}
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}
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uint64_t
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vlapic_get_cr8(const struct acrn_vlapic *vlapic)
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@ -1589,11 +1587,8 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
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dev_dbg(ACRN_DBG_LAPIC, "vlapic write offset %#x, data %#lx",
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offset, data);
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if (offset > sizeof(*lapic)) {
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return 0;
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}
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retval = 0;
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if (offset <= sizeof(*lapic)) {
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switch (offset) {
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case APIC_OFFSET_ID:
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/* Force APIC ID as read only */
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@ -1673,6 +1668,7 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
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/* Read only */
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break;
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}
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}
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return retval;
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}
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@ -1808,8 +1804,7 @@ vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest, bool phys,
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(delmode != IOAPIC_RTE_DELEXINT)) {
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic intr invalid delmode %#x", delmode);
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return;
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}
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} else {
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lowprio = (delmode == IOAPIC_RTE_DELLOPRI) || rh;
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/*
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@ -1836,18 +1831,22 @@ vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest, bool phys,
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}
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}
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}
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}
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bool
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vlapic_enabled(const struct acrn_vlapic *vlapic)
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{
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bool ret;
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const struct lapic_regs *lapic = &(vlapic->apic_page);
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if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0UL) &&
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((lapic->svr.v & APIC_SVR_ENABLE) != 0U)) {
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return true;
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ret = true;
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} else {
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return false;
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ret = false;
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}
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return ret;
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}
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static void
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@ -1910,9 +1909,7 @@ vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
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dev_dbg(ACRN_DBG_LAPIC,
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"Ignoring level trigger-mode for delivery-mode %u",
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delmode);
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return;
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}
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} else {
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/* NOTE
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* We don't check whether the vcpu is in the dest here. That means
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* all vcpus of vm will do tmr update.
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@ -1923,6 +1920,7 @@ vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
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dev_dbg(ACRN_DBG_LAPIC, "vector %u set to level-triggered", vector);
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vlapic_set_tmr(vlapic, vector, level);
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}
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}
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/*
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* @pre vcpu != NULL
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@ -1938,13 +1936,12 @@ vlapic_set_intr(struct acrn_vcpu *vcpu, uint32_t vector, bool level)
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vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR);
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic ignoring interrupt to vector %u", vector);
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return;
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}
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} else {
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if (vlapic_set_intr_ready(vlapic, vector, level) != 0) {
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vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
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}
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}
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}
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/**
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* @brief Triggers LAPIC local interrupt(LVT).
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@ -1959,7 +1956,7 @@ vlapic_set_intr(struct acrn_vcpu *vcpu, uint32_t vector, bool level)
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*
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* @pre vm != NULL
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*/
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int
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int32_t
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vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
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{
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struct acrn_vlapic *vlapic;
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@ -1968,9 +1965,8 @@ vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
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uint16_t vcpu_id = vcpu_id_arg;
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if ((vcpu_id != BROADCAST_CPU_ID) && (vcpu_id >= vm->hw.created_vcpus)) {
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return -EINVAL;
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}
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error = -EINVAL;
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} else {
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if (vcpu_id == BROADCAST_CPU_ID) {
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dmask = vm_active_cpus(vm);
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} else {
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@ -1986,6 +1982,7 @@ vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
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}
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}
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}
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}
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return error;
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}
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@ -2002,20 +1999,17 @@ vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector)
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*
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* @pre vm != NULL
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*/
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int
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int32_t
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vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg)
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{
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uint32_t delmode, vec;
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uint32_t dest;
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bool phys, rh;
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int32_t ret;
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dev_dbg(ACRN_DBG_LAPIC, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
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if ((addr & MSI_ADDR_MASK) != MSI_ADDR_BASE) {
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dev_dbg(ACRN_DBG_LAPIC, "lapic MSI invalid addr %#lx", addr);
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return -1;
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}
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if ((addr & MSI_ADDR_MASK) == MSI_ADDR_BASE) {
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/*
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* Extract the x86-specific fields from the MSI addr/msg
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* params according to the Intel Arch spec, Vol3 Ch 10.
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@ -2038,7 +2032,13 @@ vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg)
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phys ? "physical" : "logical", dest, vec);
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vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec, rh);
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return 0;
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ret = 0;
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} else {
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dev_dbg(ACRN_DBG_LAPIC, "lapic MSI invalid addr %#lx", addr);
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ret = -1;
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}
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return ret;
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}
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/* interrupt context */
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@ -2063,11 +2063,14 @@ static void vlapic_timer_expired(void *data)
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static inline bool is_x2apic_enabled(const struct acrn_vlapic *vlapic)
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{
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bool ret;
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if ((vlapic_get_apicbase(vlapic) & APICBASE_X2APIC) == 0UL) {
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return false;
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ret = false;
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} else {
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return true;
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ret = true;
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}
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return ret;
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}
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static inline uint32_t x2apic_msr_to_regoff(uint32_t msr)
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@ -2379,10 +2382,7 @@ vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
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struct lapic_reg *irr = NULL;
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pir_desc = &(vlapic->pir_desc);
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if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) != 1UL) {
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return;
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}
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if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) == 1UL) {
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pirval = 0UL;
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lapic = &(vlapic->apic_page);
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irr = &lapic->irr[0];
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@ -2432,6 +2432,7 @@ vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
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}
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}
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}
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}
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int apic_access_vmexit_handler(struct acrn_vcpu *vcpu)
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{
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@ -231,7 +231,7 @@ vlapic_intr_edge(struct acrn_vcpu *vcpu, uint32_t vector)
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*
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* @pre vm != NULL
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*/
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int vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector);
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int32_t vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vector);
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/**
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* @brief Inject MSI to target VM.
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@ -245,7 +245,7 @@ int vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t vec
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*
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* @pre vm != NULL
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*/
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int vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg);
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int32_t vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg);
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void vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest,
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bool phys, uint32_t delmode, uint32_t vec, bool rh);
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