mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2026-06-07 17:46:15 +00:00
hv:move some files to guest folder
move the following files to guest folder:
renamed: arch/x86/assign.c -> arch/x86/guest/assign.c
renamed: arch/x86/ept.c -> arch/x86/guest/ept.c
renamed: arch/x86/io_emul.c -> arch/x86/guest/io_emul.c
renamed: arch/x86/trusty.c -> arch/x86/guest/trusty.c
renamed: arch/x86/virq.c -> arch/x86/guest/virq.c
renamed: arch/x86/virtual_cr.c -> arch/x86/guest/virtual_cr.c
renamed: arch/x86/vmcs.c -> arch/x86/guest/vmcs.c
renamed: arch/x86/vmexit.c -> arch/x86/guest/vmexit.c
renamed: arch/x86/vmx_asm.S -> arch/x86/guest/vmx_asm.S
renamed: include/arch/x86/assign.h ->
include/arch/x86/guest/assign.h
renamed: include/arch/x86/io_emul.h ->
include/arch/x86/guest/io_emul.h
renamed: include/arch/x86/trusty.h ->
include/arch/x86/guest/trusty.h
renamed: include/arch/x86/virtual_cr.h ->
include/arch/x86/guest/virtual_cr.h
renamed: include/arch/x86/vmcs.h -> include/arch/x86/guest/vmcs.h
renamed: include/arch/x86/vmexit.h ->
include/arch/x86/guest/vmexit.h
After these files movement, all the files in arch/x86 are native
hardware related, and all the files in arch/x86/guest are
virtualiztion related.
Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Mingqiang Chi
committed by
Eddie Dong
Eddie Dong
parent
e9bb4267a7
commit
2b2dbe43d7
165
hypervisor/include/arch/x86/guest/assign.h
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165
hypervisor/include/arch/x86/guest/assign.h
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@@ -0,0 +1,165 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ASSIGN_H
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#define ASSIGN_H
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#include <ptdev.h>
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/**
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* @file assign.h
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*
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* @brief public APIs for Passthrough Interrupt Remapping
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*/
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/**
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* @brief VT-d
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*
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* @defgroup acrn_passthrough ACRN Passthrough
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* @{
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*/
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/**
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* @brief Acknowledge a virtual interrupt for passthrough device.
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*
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* Acknowledge a virtual legacy interrupt for a passthrough device.
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_pin virtual pin number associated with the passthrough device
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* @param[in] vpin_src ioapic or pic
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*
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* @return None
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*
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* @pre vm != NULL
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*
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*/
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void ptirq_intx_ack(struct acrn_vm *vm, uint32_t virt_pin, uint32_t vpin_src);
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/**
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* @brief MSI/MSI-x remapping for passthrough device.
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*
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* Main entry for PCI device assignment with MSI and MSI-X.
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* MSI can up to 8 vectors and MSI-X can up to 1024 Vectors.
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_bdf virtual bdf associated with the passthrough device
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* @param[in] entry_nr indicate coming vectors, entry_nr = 0 means first vector
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* @param[in] info structure used for MSI/MSI-x remapping
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*
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* @return
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* - 0: on success
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* - \p -ENODEV:
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* - for SOS, the entry already be held by others
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* - for UOS, no pre-hold mapping found.
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*
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* @pre vm != NULL
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* @pre info != NULL
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*
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*/
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int32_t ptirq_msix_remap(struct acrn_vm *vm, uint16_t virt_bdf, uint16_t entry_nr, struct ptirq_msi_info *info);
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/**
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* @brief INTx remapping for passthrough device.
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*
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* Set up the remapping of the given virtual pin for the given vm.
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* This is the main entry for PCI/Legacy device assignment with INTx, calling from vIOAPIC or vPIC.
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_pin virtual pin number associated with the passthrough device
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* @param[in] vpin_src ioapic or pic
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*
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* @return
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* - 0: on success
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* - \p -ENODEV:
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* - for SOS, the entry already be held by others
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* - for UOS, no pre-hold mapping found.
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*
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* @pre vm != NULL
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*
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*/
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int32_t ptirq_intx_pin_remap(struct acrn_vm *vm, uint32_t virt_pin, uint32_t vpin_src);
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/**
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* @brief Add an interrupt remapping entry for INTx as pre-hold mapping.
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*
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* Except sos_vm, Device Model should call this function to pre-hold ptdev intx
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* The entry is identified by phys_pin, one entry vs. one phys_pin.
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* Currently, one phys_pin can only be held by one pin source (vPIC or vIOAPIC).
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_pin virtual pin number associated with the passthrough device
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* @param[in] phys_pin physical pin number associated with the passthrough device
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* @param[in] pic_pin true for pic, false for ioapic
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*
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* @return
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* - 0: on success
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* - \p -EINVAL: invalid virt_pin value
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* - \p -ENODEV: failed to add the remapping entry
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*
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* @pre vm != NULL
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*
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*/
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int32_t ptirq_add_intx_remapping(struct acrn_vm *vm, uint32_t virt_pin, uint32_t phys_pin, bool pic_pin);
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/**
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* @brief Remove an interrupt remapping entry for INTx.
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*
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* Deactivate & remove mapping entry of the given virt_pin for given vm.
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_pin virtual pin number associated with the passthrough device
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* @param[in] pic_pin true for pic, false for ioapic
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*
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* @return None
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*
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* @pre vm != NULL
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*
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*/
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void ptirq_remove_intx_remapping(struct acrn_vm *vm, uint32_t virt_pin, bool pic_pin);
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/**
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* @brief Add interrupt remapping entry/entries for MSI/MSI-x as pre-hold mapping.
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*
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* Add pre-hold mapping of the given number of vectors between the given physical and virtual BDF for the given vm.
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* Except sos_vm, Device Model should call this function to pre-hold ptdev MSI/MSI-x.
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* The entry is identified by phys_bdf:msi_idx, one entry vs. one phys_bdf:msi_idx.
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_bdf virtual bdf associated with the passthrough device
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* @param[in] phys_bdf physical bdf associated with the passthrough device
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* @param[in] vector_count number of vectors
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*
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* @return
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* - 0: on success
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* - \p -ENODEV: failed to add the remapping entry
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*
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* @pre vm != NULL
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*
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*/
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int32_t ptirq_add_msix_remapping(struct acrn_vm *vm, uint16_t virt_bdf, uint16_t phys_bdf, uint32_t vector_count);
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/**
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* @brief Remove interrupt remapping entry/entries for MSI/MSI-x.
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*
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* Remove the mapping of given number of vectors of the given virtual BDF for the given vm.
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*
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* @param[in] vm pointer to acrn_vm
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* @param[in] virt_bdf virtual bdf associated with the passthrough device
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* @param[in] vector_count number of vectors
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*
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* @return None
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*
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* @pre vm != NULL
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*
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*/
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void ptirq_remove_msix_remapping(const struct acrn_vm *vm, uint16_t virt_bdf, uint32_t vector_count);
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/**
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* @}
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*/
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#endif /* ASSIGN_H */
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85
hypervisor/include/arch/x86/guest/io_emul.h
Normal file
85
hypervisor/include/arch/x86/guest/io_emul.h
Normal file
@@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IO_EMUL_H
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#define IO_EMUL_H
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/* Define emulated port IO index */
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#define PIC_MASTER_PIO_IDX 0U
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#define PIC_SLAVE_PIO_IDX (PIC_MASTER_PIO_IDX + 1U)
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#define PIC_ELC_PIO_IDX (PIC_SLAVE_PIO_IDX + 1U)
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#define PCI_CFGADDR_PIO_IDX (PIC_ELC_PIO_IDX + 1U)
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#define PCI_CFGDATA_PIO_IDX (PCI_CFGADDR_PIO_IDX + 1U)
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#define UART_PIO_IDX (PCI_CFGDATA_PIO_IDX + 1U)
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#define PM1A_EVT_PIO_IDX (UART_PIO_IDX + 1U)
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#define PM1A_CNT_PIO_IDX (PM1A_EVT_PIO_IDX + 1U)
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#define PM1B_EVT_PIO_IDX (PM1A_CNT_PIO_IDX + 1U)
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#define PM1B_CNT_PIO_IDX (PM1B_EVT_PIO_IDX + 1U)
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#define RTC_PIO_IDX (PM1B_CNT_PIO_IDX + 1U)
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#define EMUL_PIO_IDX_MAX (RTC_PIO_IDX + 1U)
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/**
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* @brief The handler of VM exits on I/O instructions
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*
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* @param vcpu The virtual CPU which triggers the VM exit on I/O instruction
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*/
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int32_t pio_instr_vmexit_handler(struct acrn_vcpu *vcpu);
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/**
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* @brief EPT violation handling
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*
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* @param[in] vcpu the pointer that points to vcpu data structure
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*
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* @retval -EINVAL fail to handle the EPT violation
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* @retval 0 Success to handle the EPT violation
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*/
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int32_t ept_violation_vmexit_handler(struct acrn_vcpu *vcpu);
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/**
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* @brief Allow a VM to access a port I/O range
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*
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* This API enables direct access from the given \p vm to the port I/O space
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* starting from \p port_address to \p port_address + \p nbytes - 1.
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*
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* @param vm The VM whose port I/O access permissions is to be changed
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* @param port_address The start address of the port I/O range
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* @param nbytes The size of the range, in bytes
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*/
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void allow_guest_pio_access(struct acrn_vm *vm, uint16_t port_address, uint32_t nbytes);
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/**
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* @brief Register a port I/O handler
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*
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* @param vm The VM to which the port I/O handlers are registered
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* @param pio_idx The emulated port io index
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* @param range The emulated port io range
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* @param io_read_fn_ptr The handler for emulating reads from the given range
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* @param io_write_fn_ptr The handler for emulating writes to the given range
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* @pre pio_idx < EMUL_PIO_IDX_MAX
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*/
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void register_pio_emulation_handler(struct acrn_vm *vm, uint32_t pio_idx,
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const struct vm_io_range *range, io_read_fn_t io_read_fn_ptr, io_write_fn_t io_write_fn_ptr);
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/**
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* @brief Register a MMIO handler
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*
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* This API registers a MMIO handler to \p vm before it is launched.
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*
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* @param vm The VM to which the MMIO handler is registered
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* @param read_write The handler for emulating accesses to the given range
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* @param start The base address of the range \p read_write can emulate
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* @param end The end of the range (exclusive) \p read_write can emulate
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* @param handler_private_data Handler-specific data which will be passed to \p read_write when called
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*
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* @retval 0 Registration succeeds
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* @retval -EINVAL \p read_write is NULL, \p end is not larger than \p start or \p vm has been launched
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*/
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int32_t register_mmio_emulation_handler(struct acrn_vm *vm,
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hv_mem_io_handler_t read_write, uint64_t start,
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uint64_t end, void *handler_private_data);
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#endif /* IO_EMUL_H */
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136
hypervisor/include/arch/x86/guest/trusty.h
Normal file
136
hypervisor/include/arch/x86/guest/trusty.h
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@@ -0,0 +1,136 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TRUSTY_H_
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#define TRUSTY_H_
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#define BOOTLOADER_SEED_MAX_ENTRIES 10U
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#define RPMB_MAX_PARTITION_NUMBER 6U
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#define MMC_PROD_NAME_WITH_PSN_LEN 15U
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#define BUP_MKHI_BOOTLOADER_SEED_LEN 64U
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#define TRUSTY_RAM_SIZE (16UL * 1024UL * 1024UL) /* 16 MB for now */
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/* Trusty EPT rebase gpa: 511G */
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#define TRUSTY_EPT_REBASE_GPA (511UL * 1024UL * 1024UL * 1024UL)
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#define NON_TRUSTY_PDPT_ENTRIES 511U
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/* Structure of seed info */
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struct seed_info {
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uint8_t cse_svn;
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uint8_t bios_svn;
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uint8_t padding[2];
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uint8_t seed[BUP_MKHI_BOOTLOADER_SEED_LEN];
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};
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/* Structure of key info */
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struct trusty_key_info {
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uint32_t size_of_this_struct;
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/* version info:
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0: baseline structure
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1: add ** new field
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*/
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uint32_t version;
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/* platform:
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0: Dummy (fake secret)
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1: APL (APL + ABL)
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2: ICL (ICL + SBL)
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3: ACRN (APL|ICL + SBL + ACRN)
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4: Brillo (Android Things)
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*/
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uint32_t platform;
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/* flags info:
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Bit 0: manufacturing state (0:manufacturing done;
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1:in manufacturing mode)
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Bit 1: secure boot state (0:disabled; 1: enabled)
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Bit 2: test seeds (ICL only - 0:production seeds; 1: test seeds)
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other bits all reserved as 0
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*/
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uint32_t flags;
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/* Keep 64-bit align */
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uint32_t pad1;
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/* Seed list, include useeds(user seeds) and dseed(device seeds) */
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uint32_t num_seeds;
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struct seed_info useed_list[BOOTLOADER_SEED_MAX_ENTRIES];
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struct seed_info dseed_list[BOOTLOADER_SEED_MAX_ENTRIES];
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|
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/* For ICL+ */
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/* rpmb keys, Currently HMAC-SHA256 is used in RPMB spec
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* and 256-bit (32byte) is enough. Hence only lower 32 bytes will be
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* used for now for each entry. But keep higher 32 bytes for future
|
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* extension. Note that, RPMB keys are already tied to storage device
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* serial number.If there are multiple RPMB partitions, then we will
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* get multiple available RPMB keys. And if rpmb_key[n][64] == 0,
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* then the n-th RPMB key is unavailable (Either because of no such
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* RPMB partition, or because OSloader doesn't want to share
|
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* the n-th RPMB key with Trusty)
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*/
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uint8_t rpmb_key[RPMB_MAX_PARTITION_NUMBER][64];
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/* 256-bit AES encryption key to encrypt/decrypt attestation keybox,
|
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this key should be derived from a fixed key which is RPMB seed.
|
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RPMB key (HMAC key) and this encryption key (AES key) are both
|
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derived from the same RPMB seed.
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*/
|
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uint8_t attkb_enc_key[32];
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/* For APL only */
|
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/* RPMB key is derived with dseed together with this serial number,
|
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* for ICL +, CSE directly provides the rpmb_key which is already
|
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* tied to serial number. Concatenation of emmc product name
|
||||
* with a string representation of PSN
|
||||
*/
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char serial[MMC_PROD_NAME_WITH_PSN_LEN];
|
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char pad2;
|
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};
|
||||
|
||||
struct secure_world_memory {
|
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/* The original secure world base address allocated by bootloader */
|
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uint64_t base_gpa_in_uos;
|
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/* The secure world base address of HPA */
|
||||
uint64_t base_hpa;
|
||||
/* Secure world runtime memory size */
|
||||
uint64_t length;
|
||||
};
|
||||
|
||||
struct secure_world_control {
|
||||
/* Flag indicates Secure World's state */
|
||||
struct {
|
||||
/* sworld supporting: 0(unsupported), 1(supported) */
|
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uint64_t supported : 1;
|
||||
/* sworld running status: 0(inactive), 1(active) */
|
||||
uint64_t active : 1;
|
||||
/* sworld context saving status: 0(unsaved), 1(saved) */
|
||||
uint64_t ctx_saved : 1;
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||||
uint64_t reserved : 61;
|
||||
} flag;
|
||||
/* Secure world memory structure */
|
||||
struct secure_world_memory sworld_memory;
|
||||
};
|
||||
|
||||
struct trusty_startup_param {
|
||||
uint32_t size_of_this_struct;
|
||||
uint32_t mem_size;
|
||||
uint64_t tsc_per_ms;
|
||||
uint64_t trusty_mem_base;
|
||||
uint32_t reserved;
|
||||
uint8_t padding[4];
|
||||
};
|
||||
|
||||
void switch_world(struct acrn_vcpu *vcpu, int32_t next_world);
|
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bool initialize_trusty(struct acrn_vcpu *vcpu, const struct trusty_boot_param *boot_param);
|
||||
void destroy_secure_world(struct acrn_vm *vm, bool need_clr_mem);
|
||||
void save_sworld_context(struct acrn_vcpu *vcpu);
|
||||
void restore_sworld_context(struct acrn_vcpu *vcpu);
|
||||
void trusty_set_dseed(const void *dseed, uint8_t dseed_num);
|
||||
|
||||
#endif /* TRUSTY_H_ */
|
||||
95
hypervisor/include/arch/x86/guest/virtual_cr.h
Normal file
95
hypervisor/include/arch/x86/guest/virtual_cr.h
Normal file
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VCR_H
|
||||
#define VCR_H
|
||||
|
||||
/**
|
||||
* @file virtual_cr.h
|
||||
*
|
||||
* @brief public APIs for vCR operations
|
||||
*/
|
||||
|
||||
void init_cr0_cr4_host_mask(void);
|
||||
|
||||
/**
|
||||
* @brief vCR from vcpu
|
||||
*
|
||||
* @defgroup vCR ACRN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief get vcpu CR0 value
|
||||
*
|
||||
* Get & cache target vCPU's CR0 in run_context.
|
||||
*
|
||||
* @param[in] vcpu pointer to vcpu data structure
|
||||
*
|
||||
* @return the value of CR0.
|
||||
*/
|
||||
uint64_t vcpu_get_cr0(struct acrn_vcpu *vcpu);
|
||||
|
||||
/**
|
||||
* @brief set vcpu CR0 value
|
||||
*
|
||||
* Update target vCPU's CR0 in run_context.
|
||||
*
|
||||
* @param[inout] vcpu pointer to vcpu data structure
|
||||
* @param[in] val the value set CR0
|
||||
*/
|
||||
void vcpu_set_cr0(struct acrn_vcpu *vcpu, uint64_t val);
|
||||
|
||||
/**
|
||||
* @brief get vcpu CR2 value
|
||||
*
|
||||
* Get & cache target vCPU's CR2 in run_context.
|
||||
*
|
||||
* @param[in] vcpu pointer to vcpu data structure
|
||||
*
|
||||
* @return the value of CR2.
|
||||
*/
|
||||
uint64_t vcpu_get_cr2(const struct acrn_vcpu *vcpu);
|
||||
|
||||
/**
|
||||
* @brief set vcpu CR2 value
|
||||
*
|
||||
* Update target vCPU's CR2 in run_context.
|
||||
*
|
||||
* @param[inout] vcpu pointer to vcpu data structure
|
||||
* @param[in] val the value set CR2
|
||||
*/
|
||||
void vcpu_set_cr2(struct acrn_vcpu *vcpu, uint64_t val);
|
||||
|
||||
/**
|
||||
* @brief get vcpu CR4 value
|
||||
*
|
||||
* Get & cache target vCPU's CR4 in run_context.
|
||||
*
|
||||
* @param[in] vcpu pointer to vcpu data structure
|
||||
*
|
||||
* @return the value of CR4.
|
||||
*/
|
||||
uint64_t vcpu_get_cr4(struct acrn_vcpu *vcpu);
|
||||
|
||||
/**
|
||||
* @brief set vcpu CR4 value
|
||||
*
|
||||
* Update target vCPU's CR4 in run_context.
|
||||
*
|
||||
* @param[inout] vcpu pointer to vcpu data structure
|
||||
* @param[in] val the value set CR4
|
||||
*/
|
||||
void vcpu_set_cr4(struct acrn_vcpu *vcpu, uint64_t val);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of vCR */
|
||||
|
||||
int32_t cr_access_vmexit_handler(struct acrn_vcpu *vcpu);
|
||||
|
||||
#endif /* VCR_H */
|
||||
62
hypervisor/include/arch/x86/guest/vmcs.h
Normal file
62
hypervisor/include/arch/x86/guest/vmcs.h
Normal file
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VMCS_H_
|
||||
#define VMCS_H_
|
||||
|
||||
#define VM_SUCCESS 0
|
||||
#define VM_FAIL -1
|
||||
|
||||
#ifndef ASSEMBLER
|
||||
|
||||
#define VMX_VMENTRY_FAIL 0x80000000U
|
||||
|
||||
static inline uint32_t vmx_eoi_exit(uint32_t vector)
|
||||
{
|
||||
return (VMX_EOI_EXIT0_FULL + ((vector >> 6U) * 2U));
|
||||
}
|
||||
|
||||
/* VM exit qulifications for APIC-access
|
||||
* Access type:
|
||||
* 0 = linear access for a data read during instruction execution
|
||||
* 1 = linear access for a data write during instruction execution
|
||||
* 2 = linear access for an instruction fetch
|
||||
* 3 = linear access (read or write) during event delivery
|
||||
* 10 = guest-physical access during event delivery
|
||||
* 15 = guest-physical access for an instructon fetch or during
|
||||
* instruction execution
|
||||
*/
|
||||
static inline uint64_t apic_access_type(uint64_t qual)
|
||||
{
|
||||
return ((qual >> 12U) & 0xFUL);
|
||||
}
|
||||
|
||||
static inline uint64_t apic_access_offset(uint64_t qual)
|
||||
{
|
||||
return (qual & 0xFFFUL);
|
||||
}
|
||||
|
||||
#define RFLAGS_C (1U<<0U)
|
||||
#define RFLAGS_Z (1U<<6U)
|
||||
#define RFLAGS_AC (1U<<18U)
|
||||
|
||||
#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5U)
|
||||
|
||||
void init_vmcs(struct acrn_vcpu *vcpu);
|
||||
|
||||
uint64_t vmx_rdmsr_pat(const struct acrn_vcpu *vcpu);
|
||||
int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value);
|
||||
|
||||
void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
|
||||
|
||||
static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
|
||||
{
|
||||
return vcpu->arch.cpu_mode;
|
||||
}
|
||||
|
||||
#endif /* ASSEMBLER */
|
||||
|
||||
#endif /* VMCS_H_ */
|
||||
86
hypervisor/include/arch/x86/guest/vmexit.h
Normal file
86
hypervisor/include/arch/x86/guest/vmexit.h
Normal file
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VMEXIT_H_
|
||||
#define VMEXIT_H_
|
||||
|
||||
struct vm_exit_dispatch {
|
||||
int32_t (*handler)(struct acrn_vcpu *);
|
||||
uint32_t need_exit_qualification;
|
||||
};
|
||||
|
||||
int32_t vmexit_handler(struct acrn_vcpu *vcpu);
|
||||
int32_t vmcall_vmexit_handler(struct acrn_vcpu *vcpu);
|
||||
int32_t cpuid_vmexit_handler(struct acrn_vcpu *vcpu);
|
||||
extern void vm_exit(void);
|
||||
static inline uint64_t
|
||||
vm_exit_qualification_bit_mask(uint64_t exit_qual, uint32_t msb, uint32_t lsb)
|
||||
{
|
||||
return (exit_qual &
|
||||
(((1UL << (msb + 1U)) - 1UL) - ((1UL << lsb) - 1UL)));
|
||||
}
|
||||
|
||||
/* access Control-Register Info using exit qualification field */
|
||||
static inline uint64_t vm_exit_cr_access_cr_num(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 3U, 0U) >> 0U);
|
||||
}
|
||||
|
||||
static inline uint64_t vm_exit_cr_access_type(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 5U, 4U) >> 4U);
|
||||
}
|
||||
|
||||
static inline uint64_t vm_exit_cr_access_lmsw_op(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 6U, 6U) >> 6U);
|
||||
}
|
||||
|
||||
static inline uint64_t vm_exit_cr_access_reg_idx(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 11U, 8U) >> 8U);
|
||||
}
|
||||
|
||||
static inline uint64_t vm_exit_cr_access_lmsw_src_date(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 31U, 16U) >> 16U);
|
||||
}
|
||||
|
||||
/* access IO Access Info using exit qualification field */
|
||||
static inline uint64_t vm_exit_io_instruction_size(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 2U, 0U) >> 0U);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
vm_exit_io_instruction_access_direction(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 3U, 3U) >> 3U);
|
||||
}
|
||||
|
||||
static inline uint64_t vm_exit_io_instruction_is_string(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 4U, 4U) >> 4U);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
vm_exit_io_instruction_is_rep_prefixed(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 5U, 5U) >> 5U);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
vm_exit_io_instruction_is_operand_encoding(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 6U, 6U) >> 6U);
|
||||
}
|
||||
|
||||
static inline uint64_t vm_exit_io_instruction_port_number(uint64_t exit_qual)
|
||||
{
|
||||
return (vm_exit_qualification_bit_mask(exit_qual, 31U, 16U) >> 16U);
|
||||
}
|
||||
|
||||
#endif /* VMEXIT_H_ */
|
||||
Reference in New Issue
Block a user