mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-24 22:42:53 +00:00
dm: pci: clean up assert() in pci core
Tracked-On: #3252 Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com> Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Shuo A Liu
wenlingz
parent
f8934df355
commit
2b3dedfb9b
@ -426,11 +426,10 @@ pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
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uint64_t offset;
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int bidx = (int) arg2;
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assert(bidx <= PCI_BARMAX);
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assert(pdi->bar[bidx].type == PCIBAR_MEM32 ||
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pdi->bar[bidx].type == PCIBAR_MEM64);
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assert(addr >= pdi->bar[bidx].addr &&
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addr + size <= pdi->bar[bidx].addr + pdi->bar[bidx].size);
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if (addr + size > pdi->bar[bidx].addr + pdi->bar[bidx].size) {
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pr_err("%s, Out of emulated memory range\n", __func__);
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return -ESRCH;
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}
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offset = addr - pdi->bar[bidx].addr;
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@ -473,7 +472,10 @@ pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
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{
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uint64_t base;
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assert((size & (size - 1)) == 0); /* must be a power of 2 */
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if ((size & (size - 1)) != 0) { /* must be a power of 2 */
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pr_err("%s: Cannot alloc invalid size %lld resource\n", __func__, size);
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return -1;
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}
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base = roundup2(*baseptr, size);
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@ -496,7 +498,7 @@ pci_emul_alloc_bar(struct pci_vdev *pdi, int idx, enum pcibar_type type,
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* Register (or unregister) the MMIO or I/O region associated with the BAR
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* register 'idx' of an emulated pci device.
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*/
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static void
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static int
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modify_bar_registration(struct pci_vdev *dev, int idx, int registration)
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{
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int error;
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@ -515,7 +517,7 @@ modify_bar_registration(struct pci_vdev *dev, int idx, int registration)
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* acrn-dm.
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*/
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printf("modify_bar_registration: bypass for pci-gvt\n");
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return;
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return 0;
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}
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switch (dev->bar[idx].type) {
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case PCIBAR_IO:
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@ -550,7 +552,8 @@ modify_bar_registration(struct pci_vdev *dev, int idx, int registration)
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error = EINVAL;
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break;
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}
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assert(error == 0);
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return error;
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}
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static void
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@ -624,7 +627,8 @@ update_bar_address(struct vmctx *ctx, struct pci_vdev *dev, uint64_t addr,
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dev->bar[idx].addr |= addr;
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break;
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default:
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assert(0);
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pr_err("%s: invalid bar type %d\n", __func__, type);
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return;
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}
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if (decode)
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@ -642,8 +646,6 @@ pci_emul_alloc_pbar(struct pci_vdev *pdi, int idx, uint64_t hostbase,
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int error;
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uint64_t *baseptr, limit, addr, mask, lobits, bar;
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assert(idx >= 0 && idx <= PCI_BARMAX);
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if ((size & (size - 1)) != 0)
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size = 1UL << flsl(size); /* round up to a power of 2 */
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@ -668,6 +670,10 @@ pci_emul_alloc_pbar(struct pci_vdev *pdi, int idx, uint64_t hostbase,
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lobits = PCIM_BAR_IO_SPACE;
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break;
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case PCIBAR_MEM64:
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if (idx + 1 > PCI_BARMAX) {
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pr_err("%s: invalid bar number %d for MEM64 type\n", __func__, idx);
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return -1;
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}
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/*
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* FIXME
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* Some drivers do not work well if the 64-bit BAR is allocated
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@ -703,8 +709,8 @@ pci_emul_alloc_pbar(struct pci_vdev *pdi, int idx, uint64_t hostbase,
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lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
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break;
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default:
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printf("%s: invalid bar type %d\n", __func__, type);
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assert(0);
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pr_err("%s: invalid bar type %d\n", __func__, type);
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return -1;
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}
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if (baseptr != NULL) {
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@ -722,7 +728,6 @@ pci_emul_alloc_pbar(struct pci_vdev *pdi, int idx, uint64_t hostbase,
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pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
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if (type == PCIBAR_MEM64) {
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assert(idx + 1 <= PCI_BARMAX);
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pdi->bar[idx + 1].type = PCIBAR_MEMHI64;
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pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
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}
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@ -765,8 +770,6 @@ pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen)
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int i, capoff, reallen;
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uint16_t sts;
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assert(caplen > 0);
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reallen = roundup2(caplen, 4); /* dword aligned */
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sts = pci_get_cfgdata16(dev, PCIR_STATUS);
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@ -913,19 +916,24 @@ pci_emul_deinit(struct vmctx *ctx, struct pci_vdev_ops *ops, int bus, int slot,
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}
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}
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void
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int
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pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
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{
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int mmc;
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/* Number of msi messages must be a power of 2 between 1 and 32 */
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assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
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if (((msgnum & (msgnum - 1)) != 0) || msgnum < 1 || msgnum > 32) {
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pr_err("%s: invalid number of msi messages!\n", __func__);
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return -1;
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}
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mmc = ffs(msgnum) - 1;
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bzero(msicap, sizeof(struct msicap));
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msicap->capid = PCIY_MSI;
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msicap->nextptr = nextptr;
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msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
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return 0;
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}
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int
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@ -933,9 +941,8 @@ pci_emul_add_msicap(struct pci_vdev *dev, int msgnum)
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{
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struct msicap msicap;
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pci_populate_msicap(&msicap, msgnum, 0);
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return pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
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return pci_populate_msicap(&msicap, msgnum, 0) ||
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pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
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}
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static void
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@ -943,8 +950,6 @@ pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
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uint32_t msix_tab_size)
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{
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assert(msix_tab_size % 4096 == 0);
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bzero(msixcap, sizeof(struct msixcap));
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msixcap->capid = PCIY_MSIX;
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@ -964,22 +969,23 @@ pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
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msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
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}
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static void
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static int
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pci_msix_table_init(struct pci_vdev *dev, int table_entries)
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{
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int i, table_size;
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assert(table_entries > 0);
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assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
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table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
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dev->msix.table = calloc(1, table_size);
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assert(dev->msix.table != NULL);
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if (!dev->msix.table) {
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pr_err("%s: Cannot alloc memory!\n", __func__);
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return -1;
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}
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/* set mask bit of vector control register */
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for (i = 0; i < table_entries; i++)
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dev->msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
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return 0;
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}
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int
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@ -988,8 +994,10 @@ pci_emul_add_msixcap(struct pci_vdev *dev, int msgnum, int barnum)
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uint32_t tab_size;
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struct msixcap msixcap;
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assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
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assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
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if (msgnum > MAX_MSIX_TABLE_ENTRIES) {
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pr_err("%s: Too many entries!\n", __func__);
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return -1;
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}
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tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
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@ -1003,7 +1011,8 @@ pci_emul_add_msixcap(struct pci_vdev *dev, int msgnum, int barnum)
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dev->msix.pba_offset = tab_size;
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dev->msix.pba_size = PBA_SIZE(msgnum);
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pci_msix_table_init(dev, msgnum);
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if (pci_msix_table_init(dev, msgnum) != 0)
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return -1;
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pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
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@ -1143,7 +1152,6 @@ pci_emul_capwrite(struct pci_vdev *dev, int offset, int bytes, uint32_t val)
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capoff = nextoff;
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}
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assert(offset >= capoff);
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/*
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* Capability ID and Next Capability Pointer are readonly.
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@ -1262,8 +1270,10 @@ init_pci(struct vmctx *ctx)
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if (fi->fi_name == NULL)
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continue;
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ops = pci_emul_finddev(fi->fi_name);
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assert(ops != NULL);
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if (!ops) {
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pr_warn("No driver for device [%s]\n", fi->fi_name);
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continue;
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}
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pr_notice("pci init %s\r\n", fi->fi_name);
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error = pci_emul_init(ctx, ops, bus, slot,
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func, fi);
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@ -1348,7 +1358,8 @@ init_pci(struct vmctx *ctx)
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mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
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mr.handler = pci_emul_fallback_handler;
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error = register_mem_fallback(&mr);
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assert(error == 0);
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if (error != 0)
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goto pci_emul_init_fail;
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/* ditto for the 64-bit PCI host aperture */
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bzero(&mr, sizeof(struct mem_range));
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@ -1358,7 +1369,8 @@ init_pci(struct vmctx *ctx)
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mr.size = PCI_EMUL_MEMLIMIT64 - PCI_EMUL_MEMBASE64;
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mr.handler = pci_emul_fallback_handler;
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error = register_mem_fallback(&mr);
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assert(error == 0);
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if (error != 0)
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goto pci_emul_init_fail;
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/* PCI extended config space */
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bzero(&mr, sizeof(struct mem_range));
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@ -1368,7 +1380,8 @@ init_pci(struct vmctx *ctx)
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mr.size = PCI_EMUL_ECFG_SIZE;
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mr.handler = pci_emul_ecfg_handler;
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error = register_mem(&mr);
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assert(error == 0);
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if (error != 0)
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goto pci_emul_init_fail;
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return 0;
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@ -1386,7 +1399,10 @@ pci_emul_init_fail:
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if (success_cnt-- <= 0)
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break;
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ops = pci_emul_finddev(fi->fi_name);
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assert(ops != NULL);
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if (!ops) {
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pr_warn("No driver for device [%s]\n", fi->fi_name);
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continue;
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}
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pci_emul_deinit(ctx, ops, bus, slot,
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func, fi);
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}
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@ -1441,8 +1457,10 @@ deinit_pci(struct vmctx *ctx)
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if (fi->fi_name == NULL)
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continue;
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ops = pci_emul_finddev(fi->fi_name);
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assert(ops != NULL);
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if (!ops) {
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pr_warn("No driver for device [%s]\n", fi->fi_name);
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continue;
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}
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pr_notice("pci deinit %s\n", fi->fi_name);
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pci_emul_deinit(ctx, ops, bus, slot,
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func, fi);
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@ -1559,7 +1577,6 @@ pci_bus_write_dsdt(int bus)
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goto done;
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}
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}
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assert(bi != NULL);
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/* i/o window */
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dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
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@ -1663,7 +1680,6 @@ pci_write_dsdt(void)
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int
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pci_bus_configured(int bus)
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{
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assert(bus >= 0 && bus < MAXBUSES);
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return (pci_businfo[bus] != NULL);
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}
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@ -1752,7 +1768,10 @@ pci_lintr_request(struct pci_vdev *dev)
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int bestpin, bestcount, pin;
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bi = pci_businfo[dev->bus];
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assert(bi != NULL);
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if (bi == NULL) {
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pr_err("%s: pci [%s] has wrong bus %d info!\n", __func__, dev->name, dev->bus);
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return;
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}
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/*
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* Just allocate a pin from our slot. The pin will be
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@ -1781,7 +1800,10 @@ pci_lintr_release(struct pci_vdev *dev)
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int pin;
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bi = pci_businfo[dev->bus];
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assert(bi != NULL);
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if (bi == NULL) {
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pr_err("%s: pci [%s] has wrong bus %d info!\n", __func__, dev->name, dev->bus);
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return;
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}
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si = &bi->slotinfo[dev->slot];
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@ -1802,7 +1824,10 @@ pci_lintr_route(struct pci_vdev *dev)
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return;
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bi = pci_businfo[dev->bus];
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assert(bi != NULL);
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if (bi == NULL) {
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pr_err("%s: pci [%s] has wrong bus %d info!\n", __func__, dev->name, dev->bus);
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return;
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}
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ii = &bi->slotinfo[dev->slot].si_intpins[dev->lintr.pin - 1];
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/*
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@ -1811,7 +1836,6 @@ pci_lintr_route(struct pci_vdev *dev)
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*/
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if (ii->ii_ioapic_irq == 0)
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ii->ii_ioapic_irq = ioapic_pci_alloc_irq(dev);
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assert(ii->ii_ioapic_irq > 0);
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/*
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* Attempt to allocate a PIRQ pin for this intpin if one is
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@ -1819,7 +1843,6 @@ pci_lintr_route(struct pci_vdev *dev)
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*/
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if (ii->ii_pirq_pin == 0)
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ii->ii_pirq_pin = pirq_alloc_pin(dev);
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assert(ii->ii_pirq_pin > 0);
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dev->lintr.ioapic_irq = ii->ii_ioapic_irq;
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dev->lintr.pirq_pin = ii->ii_pirq_pin;
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@ -1836,7 +1859,10 @@ pci_lintr_route(struct pci_vdev *dev)
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void
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pci_lintr_assert(struct pci_vdev *dev)
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{
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assert(dev->lintr.pin > 0);
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if (dev->lintr.pin <= 0) {
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pr_warn("%s: Invalid intr pin on dev [%s]\n", __func__, dev->name);
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return;
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}
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pthread_mutex_lock(&dev->lintr.lock);
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if (dev->lintr.state == IDLE) {
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@ -1859,7 +1885,10 @@ pci_lintr_assert(struct pci_vdev *dev)
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void
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pci_lintr_deassert(struct pci_vdev *dev)
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{
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assert(dev->lintr.pin > 0);
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if (dev->lintr.pin <= 0) {
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pr_warn("%s: Invalid intr pin on dev [%s]\n", __func__, dev->name);
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return;
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}
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pthread_mutex_lock(&dev->lintr.lock);
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if (dev->lintr.state == ASSERTED) {
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@ -2031,7 +2060,8 @@ pci_emul_cmdsts_write(struct pci_vdev *dev, int coff, uint32_t new, int bytes)
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}
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break;
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default:
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assert(0);
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pr_err("%s: invalid bar type %d\n", __func__, dev->bar[i].type);
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return;
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}
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}
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@ -2196,7 +2226,6 @@ pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
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}
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break;
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case PCIBAR_MEMHI64:
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assert(idx >= 1);
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mask = ~(dev->bar[idx - 1].size - 1);
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addr = ((uint64_t)*eax << 32) & mask;
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bar = addr >> 32;
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@ -2207,7 +2236,8 @@ pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
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}
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break;
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default:
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assert(0);
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pr_err("%s: invalid bar type %d\n", __func__, dev->bar[idx].type);
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return;
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}
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pci_set_cfgdata32(dev, coff, bar);
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@ -2307,7 +2337,6 @@ struct pci_emul_dummy {
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static int
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pci_emul_dinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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int error;
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struct pci_emul_dummy *dummy;
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dummy = calloc(1, sizeof(struct pci_emul_dummy));
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@ -2318,19 +2347,10 @@ pci_emul_dinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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pci_set_cfgdata16(dev, PCIR_VENDOR, 0x10DD);
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pci_set_cfgdata8(dev, PCIR_CLASS, 0x02);
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||||
|
||||
error = pci_emul_add_msicap(dev, PCI_EMUL_MSI_MSGS);
|
||||
assert(error == 0);
|
||||
|
||||
error = pci_emul_alloc_bar(dev, 0, PCIBAR_IO, DIOSZ);
|
||||
assert(error == 0);
|
||||
|
||||
error = pci_emul_alloc_bar(dev, 1, PCIBAR_MEM32, DMEMSZ);
|
||||
assert(error == 0);
|
||||
|
||||
error = pci_emul_alloc_bar(dev, 2, PCIBAR_MEM32, DMEMSZ);
|
||||
assert(error == 0);
|
||||
|
||||
return 0;
|
||||
return pci_emul_add_msicap(dev, PCI_EMUL_MSI_MSGS) ||
|
||||
pci_emul_alloc_bar(dev, 0, PCIBAR_IO, DIOSZ) ||
|
||||
pci_emul_alloc_bar(dev, 1, PCIBAR_MEM32, DMEMSZ) ||
|
||||
pci_emul_alloc_bar(dev, 2, PCIBAR_MEM32, DMEMSZ);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -2467,7 +2487,8 @@ pci_get_vdev_info(int slot)
|
||||
struct pci_vdev *dev = NULL;
|
||||
|
||||
bi = pci_businfo[0];
|
||||
assert(bi != NULL);
|
||||
if (bi == NULL)
|
||||
return NULL;
|
||||
|
||||
si = &bi->slotinfo[slot];
|
||||
if (si != NULL)
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
#include <stdbool.h>
|
||||
#include "types.h"
|
||||
#include "pcireg.h"
|
||||
#include "log.h"
|
||||
|
||||
#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
|
||||
#define PCI_BDF(b, d, f) (((b & 0xFF) << 8) | ((d & 0x1F) << 3) | ((f & 0x7)))
|
||||
@ -311,7 +312,7 @@ int pci_msix_table_bar(struct pci_vdev *pi);
|
||||
int pci_msix_pba_bar(struct pci_vdev *pi);
|
||||
int pci_msi_maxmsgnum(struct pci_vdev *pi);
|
||||
int pci_parse_slot(char *opt);
|
||||
void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
|
||||
int pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
|
||||
int pci_emul_add_msixcap(struct pci_vdev *pi, int msgnum, int barnum);
|
||||
int pci_emul_msix_twrite(struct pci_vdev *pi, uint64_t offset, int size,
|
||||
uint64_t value);
|
||||
@ -343,7 +344,10 @@ struct pci_vdev *pci_get_vdev_info(int slot);
|
||||
static inline void
|
||||
pci_set_cfgdata8(struct pci_vdev *dev, int offset, uint8_t val)
|
||||
{
|
||||
assert(offset <= PCI_REGMAX);
|
||||
if (offset > PCI_REGMAX) {
|
||||
pr_err("%s: out of range of PCI config space!\n", __func__);
|
||||
return;
|
||||
}
|
||||
*(uint8_t *)(dev->cfgdata + offset) = val;
|
||||
}
|
||||
|
||||
@ -359,7 +363,10 @@ pci_set_cfgdata8(struct pci_vdev *dev, int offset, uint8_t val)
|
||||
static inline void
|
||||
pci_set_cfgdata16(struct pci_vdev *dev, int offset, uint16_t val)
|
||||
{
|
||||
assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
|
||||
if ((offset > PCI_REGMAX - 1) || (offset & 1) != 0) {
|
||||
pr_err("%s: out of range of PCI config space!\n", __func__);
|
||||
return;
|
||||
}
|
||||
*(uint16_t *)(dev->cfgdata + offset) = val;
|
||||
}
|
||||
|
||||
@ -375,7 +382,10 @@ pci_set_cfgdata16(struct pci_vdev *dev, int offset, uint16_t val)
|
||||
static inline void
|
||||
pci_set_cfgdata32(struct pci_vdev *dev, int offset, uint32_t val)
|
||||
{
|
||||
assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
|
||||
if ((offset > PCI_REGMAX - 3) || (offset & 3) != 0) {
|
||||
pr_err("%s: out of range of PCI config space!\n", __func__);
|
||||
return;
|
||||
}
|
||||
*(uint32_t *)(dev->cfgdata + offset) = val;
|
||||
}
|
||||
|
||||
@ -390,7 +400,10 @@ pci_set_cfgdata32(struct pci_vdev *dev, int offset, uint32_t val)
|
||||
static inline uint8_t
|
||||
pci_get_cfgdata8(struct pci_vdev *dev, int offset)
|
||||
{
|
||||
assert(offset <= PCI_REGMAX);
|
||||
if (offset > PCI_REGMAX) {
|
||||
pr_err("%s: out of range of PCI config space!\n", __func__);
|
||||
return 0xff;
|
||||
}
|
||||
return (*(uint8_t *)(dev->cfgdata + offset));
|
||||
}
|
||||
|
||||
@ -405,7 +418,10 @@ pci_get_cfgdata8(struct pci_vdev *dev, int offset)
|
||||
static inline uint16_t
|
||||
pci_get_cfgdata16(struct pci_vdev *dev, int offset)
|
||||
{
|
||||
assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
|
||||
if ((offset > PCI_REGMAX - 1) || (offset & 1) != 0) {
|
||||
pr_err("%s: out of range of PCI config space!\n", __func__);
|
||||
return 0xffff;
|
||||
}
|
||||
return (*(uint16_t *)(dev->cfgdata + offset));
|
||||
}
|
||||
|
||||
@ -420,7 +436,10 @@ pci_get_cfgdata16(struct pci_vdev *dev, int offset)
|
||||
static inline uint32_t
|
||||
pci_get_cfgdata32(struct pci_vdev *dev, int offset)
|
||||
{
|
||||
assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
|
||||
if ((offset > PCI_REGMAX - 3) || (offset & 3) != 0) {
|
||||
pr_err("%s: out of range of PCI config space!\n", __func__);
|
||||
return 0xffffffff;
|
||||
}
|
||||
return (*(uint32_t *)(dev->cfgdata + offset));
|
||||
}
|
||||
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
|
||||
#include "macros.h"
|
||||
#include <stdint.h>
|
||||
#include <stdarg.h>
|
||||
#include <sched.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user