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HV: move dmar info definition to board.c

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The DMAR info is board specific so move the structure definition to board.c.
As a configruation file, the whole board.c could be generated by acrn-config
tool for each board.

Please note we only provide DMAR info MACROs for nuc7i7dnb board. For other
boards, ACPI_PARSE_ENABLED must be set to y in Kconfig to let hypervisor parse
DMAR info, or use acrn-config tool to generate DMAR info MACROs if user won't
enable ACPI parse code for FuSa consideration.

The patch also moves the function of get_dmar_info() to vtd.c, so dmar_info.c
could be removed.

Tracked-On: #3977

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Victor Sun 2019-10-29 19:49:52 +08:00 committed by wenlingz
parent e9a1ace1cc
commit 2ba1848980
14 changed files with 124 additions and 134 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hypervisor/Makefile
View File

@ -225,7 +225,6 @@ ifneq (,$(wildcard scenarios/$(SCENARIO_NAME)/pci_dev.c))
HW_C_SRCS += scenarios/$(SCENARIO_NAME)/pci_dev.c HW_C_SRCS += scenarios/$(SCENARIO_NAME)/pci_dev.c
endif endif
HW_C_SRCS += boot/acpi_base.c HW_C_SRCS += boot/acpi_base.c
HW_C_SRCS += boot/dmar_info.c
HW_C_SRCS += boot/cmdline.c HW_C_SRCS += boot/cmdline.c
# ACPI parsing component # ACPI parsing component
# This part should be isolated from FuSa Cert # This part should be isolated from FuSa Cert

4
hypervisor/acpi_parser/dmar_parse.c
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@ -21,6 +21,8 @@ struct find_iter_args {
typedef int32_t (*dmar_iter_t)(struct acpi_dmar_header*, void*); typedef int32_t (*dmar_iter_t)(struct acpi_dmar_header*, void*);
static uint32_t dmar_unit_cnt; static uint32_t dmar_unit_cnt;
static struct dmar_drhd drhd_info_array[MAX_DRHDS];
static struct dmar_dev_scope drhd_dev_scope[MAX_DRHDS][MAX_DRHD_DEVSCOPES];
static void *get_dmar_table(void) static void *get_dmar_table(void)
{ {
@ -237,6 +239,7 @@ int32_t parse_dmar_table(struct dmar_info *plat_dmar_info)
ASSERT(dmar_unit_cnt <= MAX_DRHDS, "parsed dmar_unit_cnt > MAX_DRHDS"); ASSERT(dmar_unit_cnt <= MAX_DRHDS, "parsed dmar_unit_cnt > MAX_DRHDS");
plat_dmar_info->drhd_count = dmar_unit_cnt; plat_dmar_info->drhd_count = dmar_unit_cnt;
plat_dmar_info->drhd_units = drhd_info_array;
for (i = 0U; i < dmar_unit_cnt; i++) { for (i = 0U; i < dmar_unit_cnt; i++) {
acpi_drhd = drhd_find_by_index(i); acpi_drhd = drhd_find_by_index(i);
@ -245,6 +248,7 @@ int32_t parse_dmar_table(struct dmar_info *plat_dmar_info)
if (acpi_drhd->flags & DRHD_FLAG_INCLUDE_PCI_ALL_MASK) if (acpi_drhd->flags & DRHD_FLAG_INCLUDE_PCI_ALL_MASK)
ASSERT((i + 1U) == dmar_unit_cnt, ASSERT((i + 1U) == dmar_unit_cnt,
"drhd with flags set should be the last one"); "drhd with flags set should be the last one");
plat_dmar_info->drhd_units[i].devices = drhd_dev_scope[i];
handle_one_drhd(acpi_drhd, &(plat_dmar_info->drhd_units[i])); handle_one_drhd(acpi_drhd, &(plat_dmar_info->drhd_units[i]));
} }

7
hypervisor/arch/x86/configs/apl-mrb/board.c
View File

@ -5,7 +5,14 @@
*/ */
#include <board.h> #include <board.h>
#include <vtd.h>
#ifndef CONFIG_ACPI_PARSE_ENABLED
#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
Or use acrn-config tool to generate platform DMAR info."
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0; uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

8
hypervisor/arch/x86/configs/apl-up2/board.c
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@ -6,6 +6,14 @@
#include <board.h> #include <board.h>
#include <msr.h> #include <msr.h>
#include <vtd.h>
#ifndef CONFIG_ACPI_PARSE_ENABLED
#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
Or use acrn-config tool to generate platform DMAR info."
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[4] = { struct platform_clos_info platform_clos_array[4] = {
{ {

7
hypervisor/arch/x86/configs/dnv-cb2/board.c
View File

@ -5,7 +5,14 @@
*/ */
#include <board.h> #include <board.h>
#include <vtd.h>
#ifndef CONFIG_ACPI_PARSE_ENABLED
#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
Or use acrn-config tool to generate platform DMAR info."
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0; uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

7
hypervisor/arch/x86/configs/generic/board.c
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@ -5,7 +5,14 @@
*/ */
#include <board.h> #include <board.h>
#include <vtd.h>
#ifndef CONFIG_ACPI_PARSE_ENABLED
#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
Or use acrn-config tool to generate platform DMAR info."
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0; uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

7
hypervisor/arch/x86/configs/icl-rvp/board.c
View File

@ -5,6 +5,13 @@
*/ */
#include <board.h> #include <board.h>
#include <vtd.h>
#ifndef CONFIG_ACPI_PARSE_ENABLED
#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
Or use acrn-config tool to generate platform DMAR info."
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0; uint16_t platform_clos_num = 0;

7
hypervisor/arch/x86/configs/nuc6cayh/board.c
View File

@ -5,7 +5,14 @@
*/ */
#include <board.h> #include <board.h>
#include <vtd.h>
#ifndef CONFIG_ACPI_PARSE_ENABLED
#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
Or use acrn-config tool to generate platform DMAR info."
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0; uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

49
hypervisor/arch/x86/configs/nuc7i7dnb/board.c
View File

@ -5,6 +5,55 @@
*/ */
#include <board.h> #include <board.h>
#include <vtd.h>
static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
{
.type = DRHD0_DEVSCOPE0_TYPE,
.id = DRHD0_DEVSCOPE0_ID,
.bus = DRHD0_DEVSCOPE0_BUS,
.devfun = DRHD0_DEVSCOPE0_PATH
},
};
static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
{
.type = DRHD1_DEVSCOPE0_TYPE,
.id = DRHD1_DEVSCOPE0_ID,
.bus = DRHD1_DEVSCOPE0_BUS,
.devfun = DRHD1_DEVSCOPE0_PATH
},
{
.type = DRHD1_DEVSCOPE1_TYPE,
.id = DRHD1_DEVSCOPE1_ID,
.bus = DRHD1_DEVSCOPE1_BUS,
.devfun = DRHD1_DEVSCOPE1_PATH
},
};
static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
{
.dev_cnt = DRHD0_DEV_CNT,
.segment = DRHD0_SEGMENT,
.flags = DRHD0_FLAGS,
.reg_base_addr = DRHD0_REG_BASE,
.ignore = DRHD0_IGNORE,
.devices = drhd0_dev_scope
},
{
.dev_cnt = DRHD1_DEV_CNT,
.segment = DRHD1_SEGMENT,
.flags = DRHD1_FLAGS,
.reg_base_addr = DRHD1_REG_BASE,
.ignore = DRHD1_IGNORE,
.devices = drhd1_dev_scope
},
};
struct dmar_info plat_dmar_info = {
.drhd_count = DRHD_COUNT,
.drhd_units = drhd_info_array,
};
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0; uint16_t platform_clos_num = 0;

59
hypervisor/arch/x86/configs/nuc7i7dnb/platform_acpi_info.h
View File

@ -43,61 +43,28 @@
#define DRHD_COUNT 2U #define DRHD_COUNT 2U
#define DRHD0_DEV_CNT 1U #define DRHD0_DEV_CNT 0x1U
#define DRHD0_SEGMENT 0U #define DRHD0_SEGMENT 0x0U
#define DRHD0_FLAGS 0U #define DRHD0_FLAGS 0x0U
#define DRHD0_REG_BASE 0xFED90000UL #define DRHD0_REG_BASE 0xFED90000UL
#define DRHD0_IGNORE false #define DRHD0_IGNORE true
#define DRHD0_DEVSCOPE0_TYPE 0x1U
#define DRHD0_DEVSCOPE0_ID 0x0U
#define DRHD0_DEVSCOPE0_BUS 0x0U #define DRHD0_DEVSCOPE0_BUS 0x0U
#define DRHD0_DEVSCOPE0_PATH 0x10U #define DRHD0_DEVSCOPE0_PATH 0x10U
#define DRHD0_DEVSCOPE1_BUS 0x0U
#define DRHD0_DEVSCOPE1_PATH 0x0U
#define DRHD0_DEVSCOPE2_BUS 0x0U
#define DRHD0_DEVSCOPE2_PATH 0x0U
#define DRHD0_DEVSCOPE3_BUS 0x0U
#define DRHD0_DEVSCOPE3_PATH 0x0U
#define DRHD1_DEV_CNT 2U #define DRHD1_DEV_CNT 0x2U
#define DRHD1_SEGMENT 0U #define DRHD1_SEGMENT 0x0U
#define DRHD1_FLAGS 1U #define DRHD1_FLAGS 0x1U
#define DRHD1_REG_BASE 0xFED91000UL #define DRHD1_REG_BASE 0xFED91000UL
#define DRHD1_IGNORE false #define DRHD1_IGNORE false
#define DRHD1_DEVSCOPE0_TYPE 0x3U
#define DRHD1_DEVSCOPE0_ID 0x2U
#define DRHD1_DEVSCOPE0_BUS 0xf0U #define DRHD1_DEVSCOPE0_BUS 0xf0U
#define DRHD1_DEVSCOPE0_PATH 0xf8U #define DRHD1_DEVSCOPE0_PATH 0xf8U
#define DRHD1_DEVSCOPE1_TYPE 0x4U
#define DRHD1_DEVSCOPE1_ID 0x0U
#define DRHD1_DEVSCOPE1_BUS 0x0U #define DRHD1_DEVSCOPE1_BUS 0x0U
#define DRHD1_DEVSCOPE1_PATH 0xf8U #define DRHD1_DEVSCOPE1_PATH 0xf8U
#define DRHD1_DEVSCOPE2_BUS 0x0U
#define DRHD1_DEVSCOPE2_PATH 0x0U
#define DRHD1_DEVSCOPE3_BUS 0x0U
#define DRHD1_DEVSCOPE3_PATH 0x0U
#define DRHD1_IOAPIC_ID 2U
#define DRHD2_DEV_CNT 0U
#define DRHD2_SEGMENT 0U
#define DRHD2_FLAGS 0U
#define DRHD2_REG_BASE 0x00UL
#define DRHD2_IGNORE false
#define DRHD2_DEVSCOPE0_BUS 0x0U
#define DRHD2_DEVSCOPE0_PATH 0x0U
#define DRHD2_DEVSCOPE1_BUS 0x0U
#define DRHD2_DEVSCOPE1_PATH 0x0U
#define DRHD2_DEVSCOPE2_BUS 0x0U
#define DRHD2_DEVSCOPE2_PATH 0x0U
#define DRHD2_DEVSCOPE3_BUS 0x0U
#define DRHD2_DEVSCOPE3_PATH 0x0U
#define DRHD3_DEV_CNT 0U
#define DRHD3_SEGMENT 0U
#define DRHD3_FLAGS 0U
#define DRHD3_REG_BASE 0x00UL
#define DRHD3_IGNORE false
#define DRHD3_DEVSCOPE0_BUS 0x0U
#define DRHD3_DEVSCOPE0_PATH 0x0U
#define DRHD3_DEVSCOPE1_BUS 0x0U
#define DRHD3_DEVSCOPE1_PATH 0x0U
#define DRHD3_DEVSCOPE2_BUS 0x0U
#define DRHD3_DEVSCOPE2_PATH 0x0U
#define DRHD3_DEVSCOPE3_BUS 0x0U
#define DRHD3_DEVSCOPE3_PATH 0x0U
#endif /* PLATFORM_ACPI_INFO_H */ #endif /* PLATFORM_ACPI_INFO_H */

13
hypervisor/arch/x86/vtd.c
View File

@ -19,6 +19,7 @@
#include <vtd.h> #include <vtd.h>
#include <timer.h> #include <timer.h>
#include <logmsg.h> #include <logmsg.h>
#include <board.h>
#include <vm_configurations.h> #include <vm_configurations.h>
#define DBG_IOMMU 0 #define DBG_IOMMU 0
@ -1329,6 +1330,18 @@ void resume_iommu(void)
do_action_for_iommus(dmar_resume); do_action_for_iommus(dmar_resume);
} }
/**
* @post return != NULL
* @post return->drhd_count > 0U
*/
static struct dmar_info *get_dmar_info(void)
{
#ifdef CONFIG_ACPI_PARSE_ENABLED
parse_dmar_table(&plat_dmar_info);
#endif
return &plat_dmar_info;
}
int32_t init_iommu(void) int32_t init_iommu(void)
{ {
int32_t ret = 0; int32_t ret = 0;

84
hypervisor/boot/dmar_info.c
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@ -1,84 +0,0 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vtd.h>
#include <platform_acpi_info.h>
static struct dmar_dev_scope drhd0_dev_scope[MAX_DRHD_DEVSCOPES] = {
{
.bus = DRHD0_DEVSCOPE0_BUS,
.devfun = DRHD0_DEVSCOPE0_PATH
},
{
.bus = DRHD0_DEVSCOPE1_BUS,
.devfun = DRHD0_DEVSCOPE1_PATH
},
{
.bus = DRHD0_DEVSCOPE2_BUS,
.devfun = DRHD0_DEVSCOPE2_PATH
},
{
.bus = DRHD0_DEVSCOPE3_BUS,
.devfun = DRHD0_DEVSCOPE3_PATH
}
};
static struct dmar_dev_scope drhd1_dev_scope[MAX_DRHD_DEVSCOPES] = {
{
.type = ACPI_DMAR_SCOPE_TYPE_IOAPIC,
.id = DRHD1_IOAPIC_ID,
.bus = DRHD1_DEVSCOPE0_BUS,
.devfun = DRHD1_DEVSCOPE0_PATH
},
{
.bus = DRHD1_DEVSCOPE1_BUS,
.devfun = DRHD1_DEVSCOPE1_PATH
},
{
.bus = DRHD1_DEVSCOPE2_BUS,
.devfun = DRHD1_DEVSCOPE2_PATH
},
{
.bus = DRHD1_DEVSCOPE3_BUS,
.devfun = DRHD1_DEVSCOPE3_PATH
}
};
static struct dmar_drhd drhd_info_array[MAX_DRHDS] = {
{
.dev_cnt = DRHD0_DEV_CNT,
.segment = DRHD0_SEGMENT,
.flags = DRHD0_FLAGS,
.reg_base_addr = DRHD0_REG_BASE,
.ignore = DRHD0_IGNORE,
.devices = drhd0_dev_scope
},
{
.dev_cnt = DRHD1_DEV_CNT,
.segment = DRHD1_SEGMENT,
.flags = DRHD1_FLAGS,
.reg_base_addr = DRHD1_REG_BASE,
.ignore = DRHD1_IGNORE,
.devices = drhd1_dev_scope
},
};
static struct dmar_info plat_dmar_info = {
.drhd_count = DRHD_COUNT,
.drhd_units = drhd_info_array,
};
/**
* @post return != NULL
* @post return->drhd_count > 0U
*/
struct dmar_info *get_dmar_info(void)
{
#ifdef CONFIG_ACPI_PARSE_ENABLED
parse_dmar_table(&plat_dmar_info);
#endif
return &plat_dmar_info;
}

1
hypervisor/include/arch/x86/board.h
View File

@ -17,6 +17,7 @@ struct platform_clos_info {
uint32_t msr_index; uint32_t msr_index;
}; };
extern struct dmar_info plat_dmar_info;
extern struct platform_clos_info platform_clos_array[]; extern struct platform_clos_info platform_clos_array[];
extern uint16_t platform_clos_num; extern uint16_t platform_clos_num;
extern const struct cpu_state_table board_cpu_state_tbl; extern const struct cpu_state_table board_cpu_state_tbl;

4
hypervisor/include/arch/x86/vtd.h
View File

@ -471,7 +471,7 @@ static inline uint16_t dma_frcd_up_sid(uint64_t up_sid)
} }
#define MAX_DRHDS DRHD_COUNT #define MAX_DRHDS DRHD_COUNT
#define MAX_DRHD_DEVSCOPES 4 #define MAX_DRHD_DEVSCOPES 16U
#define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U #define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U
#define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01U #define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01U
@ -530,8 +530,6 @@ union dmar_ir_entry {
} bits __packed; } bits __packed;
}; };
extern struct dmar_info *get_dmar_info(void);
#ifdef CONFIG_ACPI_PARSE_ENABLED #ifdef CONFIG_ACPI_PARSE_ENABLED
int32_t parse_dmar_table(struct dmar_info *plat_dmar_info); int32_t parse_dmar_table(struct dmar_info *plat_dmar_info);
#endif #endif