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hv: vmcs: minor fix about APICv feature setting

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1) Shouldn't try to set APIC-register virtualization if the physical doesn't
support APICV advanced mode.
2) Remove all APICv features VMCS setting when LAPIC is passed through to guest.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
This commit is contained in:
Li, Fei1 2019-04-18 19:46:17 +08:00 committed by wenlingz
parent 4fc2009770
commit 2c13ac7400
1 changed files with 6 additions and 4 deletions
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10
hypervisor/arch/x86/guest/vmcs.c
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@ -316,6 +316,7 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
/*Disable VM_EXIT for CR3 access*/ /*Disable VM_EXIT for CR3 access*/
value32 &= ~(VMX_PROCBASED_CTLS_CR3_LOAD | VMX_PROCBASED_CTLS_CR3_STORE); value32 &= ~(VMX_PROCBASED_CTLS_CR3_LOAD | VMX_PROCBASED_CTLS_CR3_STORE);
value32 &= ~(VMX_PROCBASED_CTLS_CR8_LOAD | VMX_PROCBASED_CTLS_CR8_STORE);
/* /*
* Disable VM_EXIT for invlpg execution. * Disable VM_EXIT for invlpg execution.
@ -330,9 +331,8 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
* guest (optional) * guest (optional)
*/ */
value32 = check_vmx_ctrl(MSR_IA32_VMX_PROCBASED_CTLS2, value32 = check_vmx_ctrl(MSR_IA32_VMX_PROCBASED_CTLS2,
VMX_PROCBASED_CTLS2_VAPIC | VMX_PROCBASED_CTLS2_EPT | VMX_PROCBASED_CTLS2_VAPIC | VMX_PROCBASED_CTLS2_EPT |
VMX_PROCBASED_CTLS2_RDTSCP | VMX_PROCBASED_CTLS2_UNRESTRICT | VMX_PROCBASED_CTLS2_RDTSCP | VMX_PROCBASED_CTLS2_UNRESTRICT);
VMX_PROCBASED_CTLS2_VAPIC_REGS);
if (vcpu->arch.vpid != 0U) { if (vcpu->arch.vpid != 0U) {
value32 |= VMX_PROCBASED_CTLS2_VPID; value32 |= VMX_PROCBASED_CTLS2_VPID;
@ -342,6 +342,7 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
if (is_apicv_advanced_feature_supported()) { if (is_apicv_advanced_feature_supported()) {
value32 |= VMX_PROCBASED_CTLS2_VIRQ; value32 |= VMX_PROCBASED_CTLS2_VIRQ;
value32 |= VMX_PROCBASED_CTLS2_VAPIC_REGS;
} else { } else {
/* /*
* This field exists only on processors that support * This field exists only on processors that support
@ -601,9 +602,10 @@ void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu)
exec_vmwrite32(VMX_TPR_THRESHOLD, 0U); exec_vmwrite32(VMX_TPR_THRESHOLD, 0U);
value32 = exec_vmread32(VMX_PROC_VM_EXEC_CONTROLS2); value32 = exec_vmread32(VMX_PROC_VM_EXEC_CONTROLS2);
value32 &= ~VMX_PROCBASED_CTLS2_VAPIC_REGS; value32 &= ~VMX_PROCBASED_CTLS2_VAPIC;
if (is_apicv_advanced_feature_supported()) { if (is_apicv_advanced_feature_supported()) {
value32 &= ~VMX_PROCBASED_CTLS2_VIRQ; value32 &= ~VMX_PROCBASED_CTLS2_VIRQ;
value32 &= ~VMX_PROCBASED_CTLS2_VAPIC_REGS;
} }
exec_vmwrite32(VMX_PROC_VM_EXEC_CONTROLS2, value32); exec_vmwrite32(VMX_PROC_VM_EXEC_CONTROLS2, value32);