diff --git a/hypervisor/arch/x86/ept.c b/hypervisor/arch/x86/ept.c
index 08e6fffc0..1d0a6c890 100644
--- a/hypervisor/arch/x86/ept.c
+++ b/hypervisor/arch/x86/ept.c
@@ -478,6 +478,12 @@ int ept_mmap(struct vm *vm, uint64_t hpa,
 	}
 
 	if (type == MAP_MEM || type == MAP_MMIO) {
+		/* EPT & VT-d share the same page tables, set SNP bit
+		 * to force snooping of PCIe devices if the page
+		 * is cachable
+		 */
+		if ((prot & IA32E_EPT_MT_MASK) != IA32E_EPT_UNCACHED)
+			prot |= IA32E_EPT_SNOOP_CTRL;
 		map_mem(&map_params, (void *)hpa,
 			(void *)gpa, size, prot);
 
diff --git a/hypervisor/arch/x86/guest/guest.c b/hypervisor/arch/x86/guest/guest.c
index 2f1dd09f1..3bed34766 100644
--- a/hypervisor/arch/x86/guest/guest.c
+++ b/hypervisor/arch/x86/guest/guest.c
@@ -554,14 +554,14 @@ static void rebuild_vm0_e820(void)
 int prepare_vm0_memmap_and_e820(struct vm *vm)
 {
 	unsigned int i;
-	uint32_t attr_wb = (MMU_MEM_ATTR_READ |
-			MMU_MEM_ATTR_WRITE   |
-			MMU_MEM_ATTR_EXECUTE |
-			MMU_MEM_ATTR_WB_CACHE);
-	uint32_t attr_uc = (MMU_MEM_ATTR_READ |
-			MMU_MEM_ATTR_WRITE   |
-			MMU_MEM_ATTR_EXECUTE |
-			MMU_MEM_ATTR_UNCACHED);
+	uint32_t attr_wb = (IA32E_EPT_R_BIT |
+				IA32E_EPT_W_BIT |
+				IA32E_EPT_X_BIT |
+				IA32E_EPT_WB);
+	uint32_t attr_uc = (IA32E_EPT_R_BIT |
+				IA32E_EPT_W_BIT |
+				IA32E_EPT_X_BIT |
+				IA32E_EPT_UNCACHED);
 	struct e820_entry *entry;
 
 
diff --git a/hypervisor/arch/x86/guest/vlapic.c b/hypervisor/arch/x86/guest/vlapic.c
index 75a4ef59a..e555e97c7 100644
--- a/hypervisor/arch/x86/guest/vlapic.c
+++ b/hypervisor/arch/x86/guest/vlapic.c
@@ -2031,8 +2031,8 @@ int vlapic_create(struct vcpu *vcpu)
 			ept_mmap(vcpu->vm,
 				apicv_get_apic_access_addr(vcpu->vm),
 				DEFAULT_APIC_BASE, CPU_PAGE_SIZE, MAP_MMIO,
-				MMU_MEM_ATTR_WRITE | MMU_MEM_ATTR_READ |
-				MMU_MEM_ATTR_UNCACHED);
+				IA32E_EPT_W_BIT | IA32E_EPT_R_BIT |
+				IA32E_EPT_UNCACHED);
 		}
 	} else {
 		/*No APICv support*/
diff --git a/hypervisor/arch/x86/mmu.c b/hypervisor/arch/x86/mmu.c
index d24f1f7e0..8e3c17a96 100644
--- a/hypervisor/arch/x86/mmu.c
+++ b/hypervisor/arch/x86/mmu.c
@@ -592,16 +592,12 @@ void init_paging(void)
 	struct map_params map_params;
 	struct e820_entry *entry;
 	uint32_t i;
-	int attr_wb = (MMU_MEM_ATTR_READ |
-			MMU_MEM_ATTR_WRITE   |
-			MMU_MEM_ATTR_EXECUTE |
-			MMU_MEM_ATTR_USER |
-			MMU_MEM_ATTR_WB_CACHE);
-	int attr_uc = (MMU_MEM_ATTR_READ |
-			MMU_MEM_ATTR_WRITE   |
-			MMU_MEM_ATTR_EXECUTE |
-			MMU_MEM_ATTR_USER |
-			MMU_MEM_ATTR_UNCACHED);
+	int attr_wb = (MMU_MEM_ATTR_BIT_READ_WRITE |
+			MMU_MEM_ATTR_BIT_USER_ACCESSIBLE |
+			MMU_MEM_ATTR_TYPE_CACHED_WB);
+	int attr_uc = (MMU_MEM_ATTR_BIT_READ_WRITE |
+			MMU_MEM_ATTR_BIT_USER_ACCESSIBLE |
+			MMU_MEM_ATTR_TYPE_UNCACHED);
 
 	pr_dbg("HV MMU Initialization");
 
@@ -637,7 +633,7 @@ void init_paging(void)
 	 */
 	modify_mem(&map_params, (void *)CONFIG_RAM_START,
 			(void *)CONFIG_RAM_START,
-			CONFIG_RAM_SIZE, attr_wb & (~MMU_MEM_ATTR_USER));
+			CONFIG_RAM_SIZE, attr_wb & (~MMU_MEM_ATTR_BIT_USER_ACCESSIBLE));
 
 	pr_dbg("Enabling MMU ");
 
@@ -684,70 +680,6 @@ bool check_continuous_hpa(struct vm *vm, uint64_t gpa, uint64_t size)
 	}
 	return true;
 
-}
-uint64_t config_page_table_attr(struct map_params *map_params, uint32_t flags)
-{
-	int  table_type = map_params->page_table_type;
-	uint64_t attr = 0;
-
-	/* Convert generic memory flags to architecture specific attributes */
-	/* Check if read access */
-	if ((flags & MMU_MEM_ATTR_READ) != 0U) {
-		/* Configure for read access */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_R_BIT : 0);
-	}
-
-	/* Check for write access */
-	if ((flags & MMU_MEM_ATTR_WRITE) != 0U)	{
-		/* Configure for write access */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_W_BIT : MMU_MEM_ATTR_BIT_READ_WRITE);
-	}
-
-	/* Check for execute access */
-	if ((flags & MMU_MEM_ATTR_EXECUTE) != 0U) {
-		/* Configure for execute (EPT only) */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_X_BIT : 0);
-	}
-
-	if ((table_type == PTT_HOST) && (flags & MMU_MEM_ATTR_USER))
-		attr |= MMU_MEM_ATTR_BIT_USER_ACCESSIBLE;
-
-	/* EPT & VT-d share the same page tables, set SNP bit
-	 * to force snooping of PCIe devices if the page
-	 * is cachable
-	 */
-	if ((flags & MMU_MEM_ATTR_UNCACHED) != MMU_MEM_ATTR_UNCACHED
-			&& table_type == PTT_EPT) {
-		attr |= IA32E_EPT_SNOOP_CTRL;
-	}
-
-	/* Check for cache / memory types */
-	if ((flags & MMU_MEM_ATTR_WB_CACHE) != 0U) {
-		/* Configure for write back cache */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_WB : MMU_MEM_ATTR_TYPE_CACHED_WB);
-	} else if ((flags & MMU_MEM_ATTR_WT_CACHE) != 0U)	{
-		/* Configure for write through cache */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_WT : MMU_MEM_ATTR_TYPE_CACHED_WT);
-	} else if ((flags & MMU_MEM_ATTR_UNCACHED) != 0U)	{
-		/* Configure for uncached */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_UNCACHED : MMU_MEM_ATTR_TYPE_UNCACHED);
-	} else if ((flags & MMU_MEM_ATTR_WC) != 0U) {
-		/* Configure for write combining */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_WC : MMU_MEM_ATTR_TYPE_WRITE_COMBINED);
-	} else {
-		/* Configure for write protected */
-		attr |= ((table_type == PTT_EPT)
-			? IA32E_EPT_WP : MMU_MEM_ATTR_TYPE_WRITE_PROTECTED);
-	}
-	return attr;
-
 }
 
 int obtain_last_page_table_entry(struct map_params *map_params,
@@ -1030,7 +962,7 @@ static int modify_paging(struct map_params *map_params, void *paddr,
 {
 	int64_t  remaining_size;
 	uint64_t adjust_size;
-	uint64_t attr;
+	uint64_t attr = flags;
 	struct entry_params entry;
 	uint64_t page_size;
 	uint64_t vaddr_end = ((uint64_t)vaddr) + size;
@@ -1051,7 +983,6 @@ static int modify_paging(struct map_params *map_params, void *paddr,
 		return -EINVAL;
 	}
 
-	attr = config_page_table_attr(map_params, flags);
 	/* Check ept misconfigurations,
 	 * rwx misconfiguration in the following conditions:
 	 * - write-only
diff --git a/hypervisor/arch/x86/mtrr.c b/hypervisor/arch/x86/mtrr.c
index 668333739..1981a4488 100755
--- a/hypervisor/arch/x86/mtrr.c
+++ b/hypervisor/arch/x86/mtrr.c
@@ -138,20 +138,20 @@ static uint32_t update_ept(struct vm *vm, uint64_t start,
 
 	switch (type) {
 	case MTRR_MEM_TYPE_WC:
-		attr = MMU_MEM_ATTR_WC;
+		attr = IA32E_EPT_WC;
 		break;
 	case MTRR_MEM_TYPE_WT:
-		attr = MMU_MEM_ATTR_WT_CACHE;
+		attr = IA32E_EPT_WT;
 		break;
 	case MTRR_MEM_TYPE_WP:
-		attr = MMU_MEM_ATTR_WP;
+		attr = IA32E_EPT_WP;
 		break;
 	case MTRR_MEM_TYPE_WB:
-		attr = MMU_MEM_ATTR_WB_CACHE;
+		attr = IA32E_EPT_WB;
 		break;
 	case MTRR_MEM_TYPE_UC:
 	default:
-		attr = MMU_MEM_ATTR_UNCACHED;
+		attr = IA32E_EPT_UNCACHED;
 	}
 
 	ept_update_mt(vm, gpa2hpa(vm, start), start, size, attr);
diff --git a/hypervisor/arch/x86/trusty.c b/hypervisor/arch/x86/trusty.c
index d3aacbb8d..e63caa4eb 100644
--- a/hypervisor/arch/x86/trusty.c
+++ b/hypervisor/arch/x86/trusty.c
@@ -117,10 +117,10 @@ static void create_secure_world_ept(struct vm *vm, uint64_t gpa_orig,
 	map_params.pml4_base = pml4_base;
 	map_mem(&map_params, (void *)hpa,
 			(void *)gpa_rebased, size,
-			(MMU_MEM_ATTR_READ |
-			 MMU_MEM_ATTR_WRITE |
-			 MMU_MEM_ATTR_EXECUTE |
-			 MMU_MEM_ATTR_WB_CACHE));
+			(IA32E_EPT_R_BIT |
+			 IA32E_EPT_W_BIT |
+			 IA32E_EPT_X_BIT |
+			 IA32E_EPT_WB));
 
 	/* Unmap trusty memory space from sos ept mapping*/
 	map_params.pml4_base = HPA2HVA(vm0->arch_vm.nworld_eptp);
@@ -166,10 +166,10 @@ void  destroy_secure_world(struct vm *vm)
 	map_mem(&map_params, (void *)vm->sworld_control.sworld_memory.base_hpa,
 			(void *)vm->sworld_control.sworld_memory.base_gpa,
 			vm->sworld_control.sworld_memory.length,
-			(MMU_MEM_ATTR_READ |
-			 MMU_MEM_ATTR_WRITE |
-			 MMU_MEM_ATTR_EXECUTE |
-			 MMU_MEM_ATTR_WB_CACHE));
+			(IA32E_EPT_R_BIT |
+			 IA32E_EPT_W_BIT |
+			 IA32E_EPT_X_BIT |
+			 IA32E_EPT_WB));
 
 }
 
diff --git a/hypervisor/common/hypercall.c b/hypervisor/common/hypercall.c
index ef7493a3d..5e738e715 100644
--- a/hypervisor/common/hypercall.c
+++ b/hypervisor/common/hypercall.c
@@ -419,23 +419,21 @@ int64_t _set_vm_memmap(struct vm *vm, struct vm *target_vm,
 	if (memmap->type != MAP_UNMAP) {
 		prot = (memmap->prot != 0) ? memmap->prot : memmap->prot_2;
 		if ((prot & MEM_ACCESS_READ) != 0U)
-			attr |= MMU_MEM_ATTR_READ;
+			attr |= IA32E_EPT_R_BIT;
 		if ((prot & MEM_ACCESS_WRITE) != 0U)
-			attr |= MMU_MEM_ATTR_WRITE;
+			attr |= IA32E_EPT_W_BIT;
 		if ((prot & MEM_ACCESS_EXEC) != 0U)
-			attr |= MMU_MEM_ATTR_EXECUTE;
+			attr |= IA32E_EPT_X_BIT;
 		if ((prot & MEM_TYPE_WB) != 0U)
-			attr |= MMU_MEM_ATTR_WB_CACHE;
+			attr |= IA32E_EPT_WB;
 		else if ((prot & MEM_TYPE_WT) != 0U)
-			attr |= MMU_MEM_ATTR_WT_CACHE;
-		else if ((prot & MEM_TYPE_UC) != 0U)
-			attr |= MMU_MEM_ATTR_UNCACHED;
+			attr |= IA32E_EPT_WT;
 		else if ((prot & MEM_TYPE_WC) != 0U)
-			attr |= MMU_MEM_ATTR_WC;
+			attr |= IA32E_EPT_WC;
 		else if ((prot & MEM_TYPE_WP) != 0U)
-			attr |= MMU_MEM_ATTR_WP;
+			attr |= IA32E_EPT_WP;
 		else
-			attr |= MMU_MEM_ATTR_UNCACHED;
+			attr |= IA32E_EPT_UNCACHED;
 	}
 
 	/* create gpa to hpa EPT mapping */
diff --git a/hypervisor/include/arch/x86/mmu.h b/hypervisor/include/arch/x86/mmu.h
index 0524fabab..40c4958ee 100644
--- a/hypervisor/include/arch/x86/mmu.h
+++ b/hypervisor/include/arch/x86/mmu.h
@@ -183,17 +183,6 @@
  * and only one of the MMU_MEM_ATTR_TYPE_xxx definitions
  */
 
-/* Generic memory attributes */
-#define     MMU_MEM_ATTR_READ                   0x00000001U
-#define     MMU_MEM_ATTR_WRITE                  0x00000002U
-#define     MMU_MEM_ATTR_EXECUTE                0x00000004U
-#define     MMU_MEM_ATTR_USER                   0x00000008U
-#define     MMU_MEM_ATTR_WB_CACHE               0x00000040U
-#define     MMU_MEM_ATTR_WT_CACHE               0x00000080U
-#define     MMU_MEM_ATTR_UNCACHED               0x00000100U
-#define     MMU_MEM_ATTR_WC                     0x00000200U
-#define     MMU_MEM_ATTR_WP                     0x00000400U
-
 /* Definitions for memory types related to x64 */
 #define     MMU_MEM_ATTR_BIT_READ_WRITE         IA32E_COMM_RW_BIT
 #define     MMU_MEM_ATTR_BIT_USER_ACCESSIBLE    IA32E_COMM_US_BIT