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HV: handle integral issue report by MISRA-C

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The main focus on: constant suffix U/UL; parameters cast like
uint32 to a uint16 variable; unify some APIs interface,
consist with the callers.

also modify some places to unify code style

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
This commit is contained in:
Minggui Cao
2018-07-12 11:47:49 +08:00
committed by lijinxia
parent 7706e5cef4
commit 2f2d108b1e
16 changed files with 113 additions and 120 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
hypervisor/include/arch/x86/guest/guest.h
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@@ -11,8 +11,8 @@
#define VM_RESUME 0
#define VM_LAUNCH 1
#define ACRN_DBG_PTIRQ 6
#define ACRN_DBG_IRQ 6
#define ACRN_DBG_PTIRQ 6U
#define ACRN_DBG_IRQ 6U
#ifndef ASSEMBLER
@@ -39,14 +39,14 @@ int32_t acrn_insert_request_wait(struct vcpu *vcpu, struct vhm_request *req);
/*
* VCPU related APIs
*/
#define ACRN_REQUEST_EXCP 0
#define ACRN_REQUEST_EVENT 1
#define ACRN_REQUEST_EXTINT 2
#define ACRN_REQUEST_NMI 3
#define ACRN_REQUEST_TMR_UPDATE 4
#define ACRN_REQUEST_EPT_FLUSH 5
#define ACRN_REQUEST_TRP_FAULT 6
#define ACRN_REQUEST_VPID_FLUSH 7 /* flush vpid tlb */
#define ACRN_REQUEST_EXCP 0U
#define ACRN_REQUEST_EVENT 1U
#define ACRN_REQUEST_EXTINT 2U
#define ACRN_REQUEST_NMI 3U
#define ACRN_REQUEST_TMR_UPDATE 4U
#define ACRN_REQUEST_EPT_FLUSH 5U
#define ACRN_REQUEST_TRP_FAULT 6U
#define ACRN_REQUEST_VPID_FLUSH 7U /* flush vpid tlb */
#define E820_MAX_ENTRIES 32U
@@ -69,13 +69,6 @@ struct vm_lu_mem_map {
uint64_t size; /* Size of map */
};
enum vm_cpu_mode {
CPU_MODE_REAL,
CPU_MODE_PROTECTED,
CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
};
/* Use # of paging level to identify paging mode */
enum vm_paging_mode {
PAGING_MODE_0_LEVEL = 0, /* Flat */

9
hypervisor/include/arch/x86/guest/vcpu.h
View File

@@ -87,6 +87,13 @@ enum vcpu_state {
VCPU_UNKNOWN_STATE,
};
enum vm_cpu_mode {
CPU_MODE_REAL,
CPU_MODE_PROTECTED,
CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
};
struct cpu_regs {
uint64_t rax;
uint64_t rbx;
@@ -202,7 +209,7 @@ struct vcpu_arch {
uint32_t exception;
/* The error number for the exception. */
int error;
uint32_t error;
} exception_info;
uint8_t lapic_mask;

2
hypervisor/include/arch/x86/irq.h
View File

@@ -99,7 +99,7 @@ void vcpu_inject_extint(struct vcpu *vcpu);
void vcpu_inject_nmi(struct vcpu *vcpu);
void vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code);
void vcpu_inject_pf(struct vcpu *vcpu, uint64_t addr, uint32_t err_code);
void vcpu_make_request(struct vcpu *vcpu, int eventid);
void vcpu_make_request(struct vcpu *vcpu, uint16_t eventid);
int vcpu_queue_exception(struct vcpu *vcpu, uint32_t vector, uint32_t err_code);
int exception_vmexit_handler(struct vcpu *vcpu);

47
hypervisor/include/arch/x86/lapic.h
View File

@@ -9,36 +9,31 @@
#define DEBUG_LAPIC 0
enum intr_lapic_icr_delivery_mode {
INTR_LAPIC_ICR_FIXED = 0x0,
INTR_LAPIC_ICR_LP = 0x1,
INTR_LAPIC_ICR_SMI = 0x2,
INTR_LAPIC_ICR_NMI = 0x4,
INTR_LAPIC_ICR_INIT = 0x5,
INTR_LAPIC_ICR_STARTUP = 0x6,
};
/* intr_lapic_icr_delivery_mode */
#define INTR_LAPIC_ICR_FIXED 0x0U
#define INTR_LAPIC_ICR_LP 0x1U
#define INTR_LAPIC_ICR_SMI 0x2U
#define INTR_LAPIC_ICR_NMI 0x4U
#define INTR_LAPIC_ICR_INIT 0x5U
#define INTR_LAPIC_ICR_STARTUP 0x6U
enum intr_lapic_icr_dest_mode {
INTR_LAPIC_ICR_PHYSICAL = 0x0,
INTR_LAPIC_ICR_LOGICAL = 0x1
};
/* intr_lapic_icr_dest_mode */
#define INTR_LAPIC_ICR_PHYSICAL 0x0U
#define INTR_LAPIC_ICR_LOGICAL 0x1U
enum intr_lapic_icr_level {
INTR_LAPIC_ICR_DEASSERT = 0x0,
INTR_LAPIC_ICR_ASSERT = 0x1,
};
/* intr_lapic_icr_level */
#define INTR_LAPIC_ICR_DEASSERT 0x0U
#define INTR_LAPIC_ICR_ASSERT 0x1U
enum intr_lapic_icr_trigger {
INTR_LAPIC_ICR_EDGE = 0x0,
INTR_LAPIC_ICR_LEVEL = 0x1,
};
/* intr_lapic_icr_trigger */
#define INTR_LAPIC_ICR_EDGE 0x0U
#define INTR_LAPIC_ICR_LEVEL 0x1U
enum intr_lapic_icr_shorthand {
INTR_LAPIC_ICR_USE_DEST_ARRAY = 0x0,
INTR_LAPIC_ICR_SELF = 0x1,
INTR_LAPIC_ICR_ALL_INC_SELF = 0x2,
INTR_LAPIC_ICR_ALL_EX_SELF = 0x3,
};
/* intr_lapic_icr_shorthand */
#define INTR_LAPIC_ICR_USE_DEST_ARRAY 0x0U
#define INTR_LAPIC_ICR_SELF 0x1U
#define INTR_LAPIC_ICR_ALL_INC_SELF 0x2U
#define INTR_LAPIC_ICR_ALL_EX_SELF 0x3U
/* Default LAPIC base */
#define LAPIC_BASE 0xFEE00000U

2
hypervisor/include/arch/x86/per_cpu.h
View File

@@ -32,7 +32,7 @@ struct per_cpu_region {
struct emul_ctxt g_inst_ctxt;
struct host_gdt gdt;
struct tss_64 tss;
enum cpu_state state;
enum cpu_state cpu_state;
uint8_t mc_stack[CONFIG_STACK_SIZE] __aligned(16);
uint8_t df_stack[CONFIG_STACK_SIZE] __aligned(16);
uint8_t sf_stack[CONFIG_STACK_SIZE] __aligned(16);

2
hypervisor/include/arch/x86/softirq.h
View File

@@ -18,6 +18,6 @@
void enable_softirq(uint16_t cpu_id);
void disable_softirq(uint16_t cpu_id);
void init_softirq(void);
void raise_softirq(int softirq_id);
void raise_softirq(uint16_t softirq_id);
void exec_softirq(void);
#endif /* SOFTIRQ_H */