hv: vtd: cleanup snoop control related code

Snoop control will not be turned on by hypervisor, delete snoop control
related code.

Tracked-On: #4831
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu 2020-05-08 01:46:26 +00:00 committed by wenlingz
parent a94c3ef763
commit 3009d9399f
3 changed files with 5 additions and 27 deletions

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@ -340,13 +340,6 @@ config MCE_ON_PSC_WORKAROUND_DISABLED
the software workaround has negative impact on performance. If all the guest OS the software workaround has negative impact on performance. If all the guest OS
kernels are trusted, this option may be set for performance. kernels are trusted, this option may be set for performance.
config IOMMU_ENFORCE_SNP
bool "IOMMU enforce snoop behavior of DMA operation"
default n
help
GPU IOMMU doesn't support snoop control capability,
To enable gvt-d,disable IOMMU snoop control by default.
config ENFORCE_TURNOFF_AC config ENFORCE_TURNOFF_AC
bool "Force to disable #AC for Split-locked Access" bool "Force to disable #AC for Split-locked Access"
default n default n

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@ -278,6 +278,11 @@ static inline uint8_t iommu_cap_rwbf(uint64_t cap)
return ((uint8_t)(cap >> 4U) & 1U); return ((uint8_t)(cap >> 4U) & 1U);
} }
static inline uint8_t iommu_ecap_sc(uint64_t ecap)
{
return ((uint8_t)(ecap >> 7U) & 1U);
}
static void dmar_unit_show_capability(struct dmar_drhd_rt *dmar_unit) static void dmar_unit_show_capability(struct dmar_drhd_rt *dmar_unit)
{ {
pr_info("dmar unit[0x%x]", dmar_unit->drhd->reg_base_addr); pr_info("dmar unit[0x%x]", dmar_unit->drhd->reg_base_addr);
@ -482,17 +487,6 @@ static int32_t dmar_register_hrhd(struct dmar_drhd_rt *dmar_unit)
if ((iommu_ecap_c(dmar_unit->ecap) == 0U) && (!dmar_unit->drhd->ignore)) { if ((iommu_ecap_c(dmar_unit->ecap) == 0U) && (!dmar_unit->drhd->ignore)) {
iommu_page_walk_coherent = false; iommu_page_walk_coherent = false;
} }
/* when the hardware support snoop control,
* to make sure snoop control is always enabled,
* the SNP filed in the leaf PTE should be set.
* How to guarantee it when EPT is used as second-level
* translation paging structures?
*/
if (iommu_ecap_sc(dmar_unit->ecap) == 0U) {
dev_dbg(DBG_LEVEL_IOMMU, "dmar uint doesn't support snoop control!");
}
dmar_disable_translation(dmar_unit); dmar_disable_translation(dmar_unit);
} }
@ -1020,10 +1014,6 @@ static int32_t iommu_attach_device(const struct iommu_domain *domain, uint8_t bu
pr_err("invalid dmar unit"); pr_err("invalid dmar unit");
ret = -EINVAL; ret = -EINVAL;
} else { } else {
if (iommu_ecap_sc(dmar_unit->ecap) == 0U) {
dev_dbg(DBG_LEVEL_IOMMU, "vm=%d add %x:%x no snoop control!", domain->vm_id, bus, devfun);
}
root_table = (struct dmar_entry *)hpa2hva(dmar_unit->root_table_addr); root_table = (struct dmar_entry *)hpa2hva(dmar_unit->root_table_addr);
root_entry = root_table + bus; root_entry = root_table + bus;

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@ -212,11 +212,6 @@ static inline uint8_t iommu_ecap_pt(uint64_t ecap)
return ((uint8_t)(ecap >> 6U) & 1U); return ((uint8_t)(ecap >> 6U) & 1U);
} }
static inline uint8_t iommu_ecap_sc(uint64_t ecap)
{
return ((uint8_t)(ecap >> 7U) & 1U);
}
static inline uint16_t iommu_ecap_iro(uint64_t ecap) static inline uint16_t iommu_ecap_iro(uint64_t ecap)
{ {
return ((uint16_t)(ecap >> 8U) & 0x3ffU); return ((uint16_t)(ecap >> 8U) & 0x3ffU);